[Mesa-dev] [PATCH 4/7] radeonsi: don't set VGT_GS_MODE as part of the GS state

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

The VS state sets it.
---
 src/gallium/drivers/radeonsi/si_state_shaders.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 78c7495..b856fc9 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -575,22 +575,20 @@ static void si_shader_gs(struct si_shader *shader)
 	unsigned gs_num_invocations = sel->gs_num_invocations;
 	struct si_pm4_state *pm4;
 	uint64_t va;
 	unsigned max_stream = sel->max_gs_stream;
 	unsigned offset;
 
 	pm4 = si_get_shader_pm4_state(shader);
 	if (!pm4)
 		return;
 
-	si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader->selector));
-
 	offset = num_components[0] * sel->gs_max_out_vertices;
 	si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
 	if (max_stream >= 1)
 		offset += num_components[1] * sel->gs_max_out_vertices;
 	si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
 	if (max_stream >= 2)
 		offset += num_components[2] * sel->gs_max_out_vertices;
 	si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
 	if (max_stream >= 3)
 		offset += num_components[3] * sel->gs_max_out_vertices;
-- 
2.7.4