[Mesa-dev] [PATCH 3/7] radeonsi: don't allow user indices with indirect draws

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

Not possible with GL and it will make future gallium rework easier.
(also it's something I wouldn't like to support)
---
 src/gallium/drivers/radeonsi/si_state_draw.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 0ada60a..9b7b52c 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1213,27 +1213,27 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 
 			util_shorten_ubyte_elts_to_userptr(&sctx->b.b, ib, 0, 0,
 							   ib->offset + start,
 							   count, ptr);
 
 			/* info->start will be added by the drawing code */
 			ib_tmp.offset -= start_offset;
 			ib_tmp.index_size = 2;
 			ib = &ib_tmp;
 		} else if (ib->user_buffer && !ib->buffer) {
-			unsigned start, count, start_offset;
+			unsigned start_offset;
 
-			si_get_draw_start_count(sctx, info, &start, &count);
-			start_offset = start * ib->index_size;
+			assert(!info->indirect);
+			start_offset = info->start * ib->index_size;
 
 			u_upload_data(ctx->stream_uploader, start_offset,
-				      count * ib->index_size,
+				      info->count * ib->index_size,
 				      sctx->screen->b.info.tcc_cache_line_size,
 				      (char*)ib->user_buffer + start_offset,
 				      &ib_tmp.offset, &ib_tmp.buffer);
 			if (!ib_tmp.buffer)
 				return;
 
 			/* info->start will be added by the drawing code */
 			ib_tmp.offset -= start_offset;
 			ib_tmp.index_size = ib->index_size;
 			ib = &ib_tmp;
-- 
2.7.4