[Mesa-dev] [PATCH 2/7] radeonsi: merge two if (indirect) statements

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_state_draw.c | 52 +++++++++++++---------------
 1 file changed, 25 insertions(+), 27 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index aa528ce..0ada60a 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -646,62 +646,36 @@ static void si_emit_draw_packets(struct si_context *sctx,
 				      (struct r600_resource *)ib->buffer,
 				      RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
 	} else {
 		/* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
 		 * so the state must be re-emitted before the next indexed draw.
 		 */
 		if (sctx->b.chip_class >= CIK)
 			sctx->last_index_size = -1;
 	}
 
-	if (!info->indirect) {
-		int base_vertex;
-
-		radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
-		radeon_emit(cs, info->instance_count);
-
-		/* Base vertex and start instance. */
-		base_vertex = info->indexed ? info->index_bias : info->start;
-
-		if (base_vertex != sctx->last_base_vertex ||
-		    sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
-		    info->start_instance != sctx->last_start_instance ||
-		    info->drawid != sctx->last_drawid ||
-		    sh_base_reg != sctx->last_sh_base_reg) {
-			radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
-			radeon_emit(cs, base_vertex);
-			radeon_emit(cs, info->start_instance);
-			radeon_emit(cs, info->drawid);
-
-			sctx->last_base_vertex = base_vertex;
-			sctx->last_start_instance = info->start_instance;
-			sctx->last_drawid = info->drawid;
-			sctx->last_sh_base_reg = sh_base_reg;
-		}
-	} else {
+	if (info->indirect) {
 		uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
 
 		assert(indirect_va % 8 == 0);
 
 		si_invalidate_draw_sh_constants(sctx);
 
 		radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
 		radeon_emit(cs, 1);
 		radeon_emit(cs, indirect_va);
 		radeon_emit(cs, indirect_va >> 32);
 
 		radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 				      (struct r600_resource *)info->indirect,
 				      RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
-	}
 
-	if (info->indirect) {
 		unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
 						    : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 
 		assert(info->indirect_offset % 4 == 0);
 
 		if (info->indexed) {
 			radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
 			radeon_emit(cs, index_va);
 			radeon_emit(cs, index_va >> 32);
 
@@ -740,20 +714,44 @@ static void si_emit_draw_packets(struct si_context *sctx,
 			radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
 					S_2C3_DRAW_INDEX_ENABLE(1) |
 					S_2C3_COUNT_INDIRECT_ENABLE(!!info->indirect_params));
 			radeon_emit(cs, info->indirect_count);
 			radeon_emit(cs, count_va);
 			radeon_emit(cs, count_va >> 32);
 			radeon_emit(cs, info->indirect_stride);
 			radeon_emit(cs, di_src_sel);
 		}
 	} else {
+		int base_vertex;
+
+		radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
+		radeon_emit(cs, info->instance_count);
+
+		/* Base vertex and start instance. */
+		base_vertex = info->indexed ? info->index_bias : info->start;
+
+		if (base_vertex != sctx->last_base_vertex ||
+		    sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
+		    info->start_instance != sctx->last_start_instance ||
+		    info->drawid != sctx->last_drawid ||
+		    sh_base_reg != sctx->last_sh_base_reg) {
+			radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
+			radeon_emit(cs, base_vertex);
+			radeon_emit(cs, info->start_instance);
+			radeon_emit(cs, info->drawid);
+
+			sctx->last_base_vertex = base_vertex;
+			sctx->last_start_instance = info->start_instance;
+			sctx->last_drawid = info->drawid;
+			sctx->last_sh_base_reg = sh_base_reg;
+		}
+
 		if (info->indexed) {
 			index_va += info->start * ib->index_size;
 
 			radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
 			radeon_emit(cs, index_max_size);
 			radeon_emit(cs, index_va);
 			radeon_emit(cs, index_va >> 32);
 			radeon_emit(cs, info->count);
 			radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
 		} else {
-- 
2.7.4