[Mesa-dev] [PATCH] radv: Use the correct pipeline for dispatches.

[Grazvydas Ignotas]

Fixes: ec15e0d30 "radv: optimise compute shader grid size emission."
Tested-by: Grazvydas Ignotas <notasas at gmail.com>

On Sat, Apr 22, 2017 at 7:42 PM, Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
wrote:

> Signed-off-by: Bas Nieuwenhuizen <basni at google.com>
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_
> buffer.c
> index 958ae6e361e..ffa7e430b2b 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -2842,7 +2842,7 @@ void radv_CmdDispatch(
>
>  MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
>         if (loc->sgpr_idx != -1) {
>                 assert(!loc->indirect);
> -               uint8_t grid_used = cmd_buffer->state.pipeline->
> shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
> +               uint8_t grid_used = cmd_buffer->state.compute_
> pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
>                 assert(loc->num_sgprs == grid_used);
>                 radeon_set_sh_reg_seq(cmd_buffer->cs,
> R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
>                 radeon_emit(cmd_buffer->cs, x);
> @@ -2881,7 +2881,7 @@ void radv_CmdDispatchIndirect(
>         struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_
> buffer->state.compute_pipeline,
>
>  MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
>         if (loc->sgpr_idx != -1) {
> -               uint8_t grid_used = cmd_buffer->state.pipeline->
> shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
> +               uint8_t grid_used = cmd_buffer->state.compute_
> pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
>                 for (unsigned i = 0; i < grid_used; ++i) {
>                         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA,
> 4, 0));
>                         radeon_emit(cmd_buffer->cs,
> COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
> @@ -2953,7 +2953,7 @@ void radv_unaligned_dispatch(
>         struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_
> buffer->state.compute_pipeline,
>
>  MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE);
>         if (loc->sgpr_idx != -1) {
> -               uint8_t grid_used = cmd_buffer->state.pipeline->
> shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
> +               uint8_t grid_used = cmd_buffer->state.compute_
> pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used;
>                 radeon_set_sh_reg_seq(cmd_buffer->cs,
> R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used);
>                 radeon_emit(cmd_buffer->cs, blocks[0]);
>                 if (grid_used > 1)
> --
> 2.12.2
>
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