[Mesa-dev] [PATCH 1/6] radeonsi: fix various CLEAR_STATE issues

[Samuel Pitoiset]

On 08/01/2017 01:23 PM, Marek Olšák wrote:
> On Tue, Aug 1, 2017 at 10:44 AM, Samuel Pitoiset
> <samuel.pitoiset at gmail.com> wrote:
>>
>>
>> On 08/01/2017 12:43 AM, Marek Olšák wrote:
>>>
>>> From: Marek Olšák <marek.olsak at amd.com>
>>>
>>> ---
>>>    src/gallium/drivers/radeonsi/si_state.c | 22 ++++++++++++++++++++++
>>>    1 file changed, 22 insertions(+)
>>>
>>> diff --git a/src/gallium/drivers/radeonsi/si_state.c
>>> b/src/gallium/drivers/radeonsi/si_state.c
>>> index 7dadc4a..c151a98 100644
>>> --- a/src/gallium/drivers/radeonsi/si_state.c
>>> +++ b/src/gallium/drivers/radeonsi/si_state.c
>>> @@ -4542,24 +4542,46 @@ static void si_init_config(struct si_context
>>> *sctx)
>>>                          si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
>>>                                         raster_config);
>>>                          if (sctx->b.chip_class >= CIK)
>>>                                  si_pm4_set_reg(pm4,
>>> R_028354_PA_SC_RASTER_CONFIG_1,
>>>                                                 raster_config_1);
>>>                  } else {
>>>                          si_write_harvested_raster_configs(sctx, pm4,
>>> raster_config, raster_config_1);
>>>                  }
>>>          }
>>>    +     /* CLEAR_STATE doesn't clear these correctly on certain
>>> generations.
>>> +        * I don't know why. Deduced by trial and error.
>>> +        */
>>> +       if (sctx->b.chip_class <= CIK) {
>>> +               si_pm4_set_reg(pm4,
>>> R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
>>> +               si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL,
>>> S_028204_WINDOW_OFFSET_DISABLE(1));
>>> +               si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL,
>>> S_028240_WINDOW_OFFSET_DISABLE(1));
>>> +               si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
>>> +                              S_028244_BR_X(16384) |
>>> S_028244_BR_Y(16384));
>>> +               si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
>>> +               si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
>>> +                              S_028034_BR_X(16384) |
>>> S_028034_BR_Y(16384));
>>> +       }
>>> +
>>
>>
>> After grepping the clearstate_*.h files, they seem to be correctly
>> initialized, did I miss something?
> 
> The workaround above is undocumented hardware territory. The one below
> is documented.

Oh okay, I see. :)

Looks good to me then.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>

> 
>>
>>
>>>          if (sctx->b.chip_class >= GFX9) {
>>>                  si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
>>>                  si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
>>>                  si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
>>> +       } else {
>>> +               /* These registers, when written, also overwrite the
>>> CLEAR_STATE
>>> +                * context, so we can't rely on CLEAR_STATE setting them.
>>> +                * It would be an issue if there was another UMD changing
>>> them.
>>> +                */
>>> +               si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
>>> +               si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
>>> +               si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
>>>          }
>>>          if (sctx->b.chip_class >= CIK) {
>>>                  if (sctx->b.chip_class >= GFX9) {
>>>                          si_pm4_set_reg(pm4,
>>> R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
>>>                  } else {
>>>                          si_pm4_set_reg(pm4,
>>> R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
>>>                          si_pm4_set_reg(pm4,
>>> R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
>>>                          si_pm4_set_reg(pm4,
>>> R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
>>>
> 
> Marek
>