[Mesa-dev] [PATCH] i965: Simplify MOCS mashing in genX_state_upload.c.
lionel.g.landwerlin at intel.com
Thu Aug 24 15:22:01 UTC 2017
On 24/08/17 16:15, Kenneth Graunke wrote:
> On Thursday, August 24, 2017 4:04:26 AM PDT Lionel Landwerlin wrote:
>> Looks good, but it looks like you could replace an additional one in
> That one is a bit weird - it uses 0 on Gen8+. I've wondered about that,
> actually - the docs claim that you must use 0 - but at least on Skylake,
> 0 is an entry in the table that means uncached. So is the requirement
> that the bits be 0, or the requirement that you bypass caching?
> Things we'll never know I guess. I'm not sure if it matters, though,
> since it's just pulling the data into a segment of the L3 anyway...so
> it's only read one time...
> At any rate, I left it open coded because it's different than the others.
>> Also why not name it GEN_MOCS ? (so it's a bit more consistent with
>> other macros defined per gen).
> I like this. Changed locally.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
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