[Mesa-dev] [PATCH 2/2] i965: compute scratch space size correctly for Gen9

[Kenneth Graunke]

On Tuesday, December 12, 2017 4:17:27 AM PST kevin.rogovin at intel.com wrote:
> From: Kevin Rogovin <kevin.rogovin at intel.com>
> 
> Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_program.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
> index 6aa4100..1ae0aa0 100644
> --- a/src/mesa/drivers/dri/i965/brw_program.c
> +++ b/src/mesa/drivers/dri/i965/brw_program.c
> @@ -368,9 +368,13 @@ brw_alloc_stage_scratch(struct brw_context *brw,
>         *
>         * According to the other driver team, this applies to compute shaders
>         * as well.  This is not currently documented at all.
> +       *
> +       * brw->screen->subslice_total is the TOTAL number of subslices
> +       * and we wish to view that there are 4 subslices per slice
> +       * instead of the actual number of subslices per slice.
>         */
>        if (devinfo->gen >= 9)
> -         subslices = 4;
> +         subslices = 4 * brw->screen->devinfo.num_slices;
>  
>        /* WaCSScratchSize:hsw
>         *
> 

Thank you!  I'd meant to clean up the nonsense in patch 1 a while ago,
but I guess I got distracted.  Good catch on the bug, too...

First is R-b, and this one gets:

    Fixes: 8ecdbb61360 "i965: Pretend there are 4 subslices for compute shader threads on Gen9+."
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104005
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

Both are now pushed:

To ssh://git.freedesktop.org/git/mesa/mesa
   7469966ed2a..b1ce812c514  master -> master

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