[Mesa-dev] [PATCH] radv/gfx9: add 3d sampler image->buffer copy shader. (v2)
Alex Smith
asmith at feralinteractive.com
Wed Dec 20 14:49:40 UTC 2017
Tested-by: Alex Smith <asmith at feralinteractive.com>
Fixes 3D texture contents being captured incorrectly in RenderDoc for me.
On 19 December 2017 at 07:36, Dave Airlie <airlied at gmail.com> wrote:
> From: Dave Airlie <airlied at redhat.com>
>
> On GFX9 we must access 3D textures with 3D samplers AFAICS.
>
> This fixes:
> dEQP-VK.api.image_clearing.core.clear_color_image.3d.single_layer
>
> on GFX9 for me.
>
> v2: fixes a bunch of other tests as well.
>
> v1.1: fix tex->sampler_dim to dim
> v2: send layer in from outside
>
> Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
> Signed-off-by: Dave Airlie <airlied at redhat.com>
> ---
> src/amd/vulkan/radv_meta_bufimage.c | 87 ++++++++++++++++++++++++++++++
> -------
> src/amd/vulkan/radv_private.h | 1 +
> 2 files changed, 72 insertions(+), 16 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_meta_bufimage.c
> b/src/amd/vulkan/radv_meta_bufimage.c
> index dfd99aa75f..4a61beef18 100644
> --- a/src/amd/vulkan/radv_meta_bufimage.c
> +++ b/src/amd/vulkan/radv_meta_bufimage.c
> @@ -29,11 +29,15 @@
> * Compute queue: implementation also of buffer->image, image->image, and
> image clear.
> */
>
> +/* GFX9 needs to use a 3D sampler to access 3D resources, so the shader
> has the options
> + * for that.
> + */
> static nir_shader *
> -build_nir_itob_compute_shader(struct radv_device *dev)
> +build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d)
> {
> nir_builder b;
> - const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_
> SAMPLER_DIM_2D,
> + enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D :
> GLSL_SAMPLER_DIM_2D;
> + const struct glsl_type *sampler_type = glsl_sampler_type(dim,
> false,
> false,
>
> GLSL_TYPE_FLOAT);
> @@ -42,7 +46,7 @@ build_nir_itob_compute_shader(struct radv_device *dev)
> false,
>
> GLSL_TYPE_FLOAT);
> nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE,
> NULL);
> - b.shader->info.name = ralloc_strdup(b.shader, "meta_itob_cs");
> + b.shader->info.name = ralloc_strdup(b.shader, is_3d ?
> "meta_itob_cs_3d" : "meta_itob_cs");
> b.shader->info.cs.local_size[0] = 16;
> b.shader->info.cs.local_size[1] = 16;
> b.shader->info.cs.local_size[2] = 1;
> @@ -69,32 +73,46 @@ build_nir_itob_compute_shader(struct radv_device *dev)
>
> nir_intrinsic_instr *offset = nir_intrinsic_instr_create(b.shader,
> nir_intrinsic_load_push_constant);
> nir_intrinsic_set_base(offset, 0);
> - nir_intrinsic_set_range(offset, 12);
> + nir_intrinsic_set_range(offset, 16);
> offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
> - offset->num_components = 2;
> - nir_ssa_dest_init(&offset->instr, &offset->dest, 2, 32, "offset");
> + offset->num_components = 3;
> + nir_ssa_dest_init(&offset->instr, &offset->dest, 3, 32, "offset");
> nir_builder_instr_insert(&b, &offset->instr);
>
> nir_intrinsic_instr *stride = nir_intrinsic_instr_create(b.shader,
> nir_intrinsic_load_push_constant);
> nir_intrinsic_set_base(stride, 0);
> - nir_intrinsic_set_range(stride, 12);
> - stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
> + nir_intrinsic_set_range(stride, 16);
> + stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12));
> stride->num_components = 1;
> nir_ssa_dest_init(&stride->instr, &stride->dest, 1, 32, "stride");
> nir_builder_instr_insert(&b, &stride->instr);
>
> nir_ssa_def *img_coord = nir_iadd(&b, global_id,
> &offset->dest.ssa);
>
> + nir_ssa_def *img_coord_3d = NULL;
> +
> + if (is_3d) {
> + nir_ssa_def *chans[3];
> +
> + chans[0] = nir_channel(&b, img_coord, 0);
> + chans[1] = nir_channel(&b, img_coord, 1);
> + chans[2] = nir_channel(&b, img_coord, 2);
> + img_coord_3d = nir_vec(&b, chans, 3);
> + }
> +
> nir_tex_instr *tex = nir_tex_instr_create(b.shader, 2);
> - tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
> + tex->sampler_dim = dim;
> tex->op = nir_texop_txf;
> tex->src[0].src_type = nir_tex_src_coord;
> - tex->src[0].src = nir_src_for_ssa(nir_channels(&b, img_coord,
> 0x3));
> + if (is_3d)
> + tex->src[0].src = nir_src_for_ssa(nir_channels(&b,
> img_coord_3d, 0x7));
> + else
> + tex->src[0].src = nir_src_for_ssa(nir_channels(&b,
> img_coord, 0x3));
> tex->src[1].src_type = nir_tex_src_lod;
> tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
> tex->dest_type = nir_type_float;
> tex->is_array = false;
> - tex->coord_components = 2;
> + tex->coord_components = is_3d ? 3 : 2;
> tex->texture = nir_deref_var_create(tex, input_img);
> tex->sampler = NULL;
>
> @@ -126,8 +144,11 @@ radv_device_init_meta_itob_state(struct radv_device
> *device)
> {
> VkResult result;
> struct radv_shader_module cs = { .nir = NULL };
> + struct radv_shader_module cs_3d = { .nir = NULL };
>
> - cs.nir = build_nir_itob_compute_shader(device);
> + cs.nir = build_nir_itob_compute_shader(device, false);
> + if (device->physical_device->rad_info.chip_class >= GFX9)
> + cs_3d.nir = build_nir_itob_compute_shader(device, true);
>
> /*
> * two descriptors one for the image being sampled
> @@ -168,7 +189,7 @@ radv_device_init_meta_itob_state(struct radv_device
> *device)
> .setLayoutCount = 1,
> .pSetLayouts = &device->meta_state.itob.img_ds_layout,
> .pushConstantRangeCount = 1,
> - .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT,
> 0, 12},
> + .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT,
> 0, 16},
> };
>
> result = radv_CreatePipelineLayout(radv_device_to_handle(device),
> @@ -202,10 +223,36 @@ radv_device_init_meta_itob_state(struct radv_device
> *device)
> if (result != VK_SUCCESS)
> goto fail;
>
> + if (device->physical_device->rad_info.chip_class >= GFX9) {
> + VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d
> = {
> + .sType = VK_STRUCTURE_TYPE_PIPELINE_
> SHADER_STAGE_CREATE_INFO,
> + .stage = VK_SHADER_STAGE_COMPUTE_BIT,
> + .module = radv_shader_module_to_handle(&cs_3d),
> + .pName = "main",
> + .pSpecializationInfo = NULL,
> + };
> +
> + VkComputePipelineCreateInfo vk_pipeline_info_3d = {
> + .sType = VK_STRUCTURE_TYPE_COMPUTE_
> PIPELINE_CREATE_INFO,
> + .stage = pipeline_shader_stage_3d,
> + .flags = 0,
> + .layout = device->meta_state.itob.img_p_layout,
> + };
> +
> + result = radv_CreateComputePipelines(
> radv_device_to_handle(device),
> +
> radv_pipeline_cache_to_handle(&device->meta_state.cache),
> + 1,
> &vk_pipeline_info_3d, NULL,
> +
> &device->meta_state.itob.pipeline_3d);
> + if (result != VK_SUCCESS)
> + goto fail;
> + ralloc_free(cs_3d.nir);
> + }
> ralloc_free(cs.nir);
> +
> return VK_SUCCESS;
> fail:
> ralloc_free(cs.nir);
> + ralloc_free(cs_3d.nir);
> return result;
> }
>
> @@ -221,6 +268,9 @@ radv_device_finish_meta_itob_state(struct radv_device
> *device)
> &state->alloc);
> radv_DestroyPipeline(radv_device_to_handle(device),
> state->itob.pipeline, &state->alloc);
> + if (device->physical_device->rad_info.chip_class >= GFX9)
> + radv_DestroyPipeline(radv_device_to_handle(device),
> + state->itob.pipeline_3d,
> &state->alloc);
> }
>
> static nir_shader *
> @@ -792,7 +842,7 @@ create_iview(struct radv_cmd_buffer *cmd_buffer,
> &(VkImageViewCreateInfo) {
> .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_
> CREATE_INFO,
> .image =
> radv_image_to_handle(surf->image),
> - .viewType =
> VK_IMAGE_VIEW_TYPE_2D,
> + .viewType =
> radv_meta_get_view_type(surf->image),
> .format = surf->format,
> .subresourceRange = {
> .aspectMask =
> surf->aspect_mask,
> @@ -878,18 +928,23 @@ radv_meta_image_to_buffer(struct radv_cmd_buffer
> *cmd_buffer,
> itob_bind_descriptors(cmd_buffer, &src_view, &dst_view);
>
>
> + if (device->physical_device->rad_info.chip_class >= GFX9 &&
> + src->image->type == VK_IMAGE_TYPE_3D)
> + pipeline = cmd_buffer->device->meta_
> state.itob.pipeline_3d;
> +
> radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
> VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
>
> for (unsigned r = 0; r < num_rects; ++r) {
> - unsigned push_constants[3] = {
> + unsigned push_constants[4] = {
> rects[r].src_x,
> rects[r].src_y,
> + src->layer,
> dst->pitch
> };
> radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_
> buffer),
> device->meta_state.itob.img_p_
> layout,
> - VK_SHADER_STAGE_COMPUTE_BIT, 0, 12,
> + VK_SHADER_STAGE_COMPUTE_BIT, 0, 16,
> push_constants);
>
> radv_unaligned_dispatch(cmd_buffer, rects[r].width,
> rects[r].height, 1);
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index 9ef1f78932..63e8b50053 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -416,6 +416,7 @@ struct radv_meta_state {
> VkPipelineLayout img_p_layout;
> VkDescriptorSetLayout img_ds_layout;
> VkPipeline pipeline;
> + VkPipeline pipeline_3d;
> } itob;
> struct {
> VkPipelineLayout img_p_layout;
> --
> 2.14.3
>
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> mesa-dev at lists.freedesktop.org
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>
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