[Mesa-dev] [PATCH] nv50/ir: convert an ATOM.EXCH without a destination into a store

[Ilia Mirkin]

Not easily, I don't have a blob setup. However right now, on SM35, we
are emitting ATOM.EXCH R0, [Rx], Ry, which as you'll note, overwrites
R0. Oops.

On Fri, Feb 10, 2017 at 5:24 AM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> Can you double check what the blob do in this scenario?
>
>
> On 02/10/2017 07:59 AM, Ilia Mirkin wrote:
>>
>> On SM35 there does not appear to be a way to emit a ATOM.EXCH with a
>> null destination. This should be functionally equivalent to a plain
>> store however, so just do that.
>>
>> Fixes GL45-CTS.compute_shader.atomic-case2 on SM35.
>>
>> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
>> ---
>>  src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>> index d79e87d..79403c9 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>> @@ -3549,6 +3549,11 @@ DeadCodeElim::visit(BasicBlock *bb)
>>               i->op == OP_SUREDP ||
>>               i->op == OP_SUREDB) {
>>              i->setDef(0, NULL);
>> +            if (i->op == OP_ATOM && i->subOp == NV50_IR_SUBOP_ATOM_EXCH)
>> {
>> +               i->cache = CACHE_CV;
>> +               i->op = OP_STORE;
>> +               i->subOp = 0;
>> +            }
>>           } else if (i->op == OP_LOAD && i->subOp ==
>> NV50_IR_SUBOP_LOAD_LOCKED) {
>>              i->setDef(0, i->getDef(1));
>>              i->setDef(1, NULL);
>>
>