[Mesa-dev] [PATCH 14/18] gallium/radeon: use TCC line size as alignment in other places

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeon/r600_buffer_common.c | 3 ++-
 src/gallium/drivers/radeon/r600_pipe_common.c   | 3 ++-
 src/gallium/drivers/radeonsi/si_compute.c       | 3 ++-
 src/gallium/drivers/radeonsi/si_descriptors.c   | 5 +++--
 4 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index 9e5a8a6..e37e36f 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -362,21 +362,22 @@ static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 
 		/* Check if mapping this buffer would cause waiting for the GPU. */
 		if (r600_rings_is_buffer_referenced(rctx, rbuffer->buf, RADEON_USAGE_READWRITE) ||
 		    !rctx->ws->buffer_wait(rbuffer->buf, 0, RADEON_USAGE_READWRITE)) {
 			/* Do a wait-free write-only transfer using a temporary buffer. */
 			unsigned offset;
 			struct r600_resource *staging = NULL;
 
 			u_upload_alloc(ctx->stream_uploader, 0,
                                        box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
-				       256, &offset, (struct pipe_resource**)&staging,
+				       rctx->screen->info.tcc_cache_line_size,
+				       &offset, (struct pipe_resource**)&staging,
                                        (void**)&data);
 
 			if (staging) {
 				data += box->x % R600_MAP_BUFFER_ALIGNMENT;
 				return r600_buffer_get_transfer(ctx, resource, usage, box,
 								ptransfer, data, staging, offset);
 			}
 		} else {
 			/* At this point, the buffer is always idle (we checked it above). */
 			usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index 8405c5e..d573b39 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -186,21 +186,22 @@ void r600_draw_rectangle(struct blitter_context *blitter,
 	viewport.scale[1] = 1.0f;
 	viewport.scale[2] = 1.0f;
 	viewport.translate[0] = 0.0f;
 	viewport.translate[1] = 0.0f;
 	viewport.translate[2] = 0.0f;
 	rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
 
 	/* Upload vertices. The hw rectangle has only 3 vertices,
 	 * I guess the 4th one is derived from the first 3.
 	 * The vertex specification should match u_blitter's vertex element state. */
-	u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24, 256,
+	u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
+		       rctx->screen->info.tcc_cache_line_size,
                        &offset, &buf, (void**)&vb);
 	if (!buf)
 		return;
 
 	vb[0] = x1;
 	vb[1] = y1;
 	vb[2] = depth;
 	vb[3] = 1;
 
 	vb[8] = x1;
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index aae651c..381837c 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -558,21 +558,22 @@ static void si_upload_compute_input(struct si_context *sctx,
 	unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
 	uint32_t kernel_args_offset = 0;
 	uint32_t *kernel_args;
 	void *kernel_args_ptr;
 	uint64_t kernel_args_va;
 	unsigned i;
 
 	/* The extra num_work_size_bytes are for work group / work item size information */
 	kernel_args_size = program->input_size + num_work_size_bytes;
 
-	u_upload_alloc(sctx->b.b.stream_uploader, 0, kernel_args_size, 256,
+	u_upload_alloc(sctx->b.b.stream_uploader, 0, kernel_args_size,
+		       sctx->screen->b.info.tcc_cache_line_size,
 		       &kernel_args_offset,
 		       (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
 
 	kernel_args = (uint32_t*)kernel_args_ptr;
 	kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
 
 	if (!code_object) {
 		for (i = 0; i < 3; i++) {
 			kernel_args[i] = info->grid[i];
 			kernel_args[i + 3] = info->grid[i] * info->block[i];
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 4f2dbbb..b4f1fbf 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -130,22 +130,23 @@ static void si_init_descriptors(struct si_descriptors *desc,
 static void si_release_descriptors(struct si_descriptors *desc)
 {
 	r600_resource_reference(&desc->buffer, NULL);
 	FREE(desc->list);
 }
 
 static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
 			 unsigned *out_offset, struct r600_resource **out_buf) {
 	uint64_t va;
 
-	u_suballocator_alloc(sctx->ce_suballocator, size, 64, out_offset,
-			     (struct pipe_resource**)out_buf);
+	u_suballocator_alloc(sctx->ce_suballocator, size,
+			     sctx->screen->b.info.tcc_cache_line_size,
+			     out_offset, (struct pipe_resource**)out_buf);
 	if (!out_buf)
 			return false;
 
 	va = (*out_buf)->gpu_address + *out_offset;
 
 	radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
 	radeon_emit(sctx->ce_ib, ce_offset);
 	radeon_emit(sctx->ce_ib, size / 4);
 	radeon_emit(sctx->ce_ib, va);
 	radeon_emit(sctx->ce_ib, va >> 32);
-- 
2.7.4