[Mesa-dev] [PATCH 13/18] radeonsi: use a clever alignment for index buffer uploads

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_state_draw.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index ca28f50..8fed61a 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1041,28 +1041,30 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 		/* Initialize the index buffer struct. */
 		pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
 		ib.user_buffer = sctx->index_buffer.user_buffer;
 		ib.index_size = sctx->index_buffer.index_size;
 		ib.offset = sctx->index_buffer.offset;
 
 		/* Translate or upload, if needed. */
 		/* 8-bit indices are supported on VI. */
 		if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
 			struct pipe_resource *out_buffer = NULL;
-			unsigned out_offset, start, count, start_offset;
+			unsigned out_offset, start, count, start_offset, size;
 			void *ptr;
 
 			si_get_draw_start_count(sctx, info, &start, &count);
 			start_offset = start * 2;
+			size = count * 2;
 
 			u_upload_alloc(ctx->stream_uploader, start_offset,
-                                       count * 2, 256,
+				       size,
+				       si_optimal_tcc_alignment(sctx, size),
 				       &out_offset, &out_buffer, &ptr);
 			if (!out_buffer) {
 				pipe_resource_reference(&ib.buffer, NULL);
 				return;
 			}
 
 			util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
 							   ib.offset + start_offset,
 							   count, ptr);
 
@@ -1072,22 +1074,23 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 			/* info->start will be added by the drawing code */
 			ib.offset = out_offset - start_offset;
 			ib.index_size = 2;
 		} else if (ib.user_buffer && !ib.buffer) {
 			unsigned start, count, start_offset;
 
 			si_get_draw_start_count(sctx, info, &start, &count);
 			start_offset = start * ib.index_size;
 
 			u_upload_data(ctx->stream_uploader, start_offset,
-                                      count * ib.index_size,
-				      256, (char*)ib.user_buffer + start_offset,
+				      count * ib.index_size,
+				      sctx->screen->b.info.tcc_cache_line_size,
+				      (char*)ib.user_buffer + start_offset,
 				      &ib.offset, &ib.buffer);
 			if (!ib.buffer)
 				return;
 			/* info->start will be added by the drawing code */
 			ib.offset -= start_offset;
 		} else if (sctx->b.chip_class <= CIK &&
 			   r600_resource(ib.buffer)->TC_L2_dirty) {
 			/* VI reads index buffers through TC L2, so it doesn't
 			 * need this. */
 			sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
-- 
2.7.4