[Mesa-dev] [PATCH 12/18] radeonsi: use a clever alignment for descriptor uploads

Nicolai Hähnle nhaehnle at gmail.com
Fri Feb 17 09:07:33 UTC 2017

On 16.02.2017 23:16, Marek Olšák wrote:
> On Thu, Feb 16, 2017 at 4:17 PM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
>> On 16.02.2017 13:53, Marek Olšák wrote:
>>> From: Marek Olšák <marek.olsak at amd.com>
>>> Non-VBO descriptors won't be smaller than the cache line, so simply use
>>> the cache line size.
>> What about SSBOs? Those are just 16 bytes.
>> Also, shader images are just 32 bytes (though we may have to bump this to 64
> We always upload the whole list for non-VBO descriptors, which is
> num_slot * slot_size. That's a lot more than a cache line. We could
> certainly optimize this for both CE and non-CE paths. The CE path
> evicts more cache lines needlessly, while the non-CE path has to
> upload more data.
> Since only the necessary number of VBO descriptors is uploaded, we can
> hang the hardware if the vertex shader is using more inputs than the
> vertex element state, which luckily can't happen with st/mesa.

Ah, thanks for the reminder. This patch has my R-b as well.

>> bytes for multisample image support -- except that it's unclear how to write
>> to a multisample shader image while keeping the FMASK).
> I wouldn't like to support MSAA image stores.

We may not have a choice if games expect to be able to use shader image 
functionality with MSAA. But I agree that it's ugly.


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