[Mesa-dev] [PATCH 08/16] i965/dri2: Add end-of-pipe-sync after color resolves
Topi Pohjolainen
topi.pohjolainen at gmail.com
Fri Feb 17 19:32:11 UTC 2017
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_context.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index bb84102..75d4920 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1476,7 +1476,10 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
if (rb->mt->num_samples <= 1) {
assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
rb->layer_count == 1);
- intel_miptree_resolve_color(brw, rb->mt, 0, 0, 1, 0);
+ if (intel_miptree_resolve_color(brw, rb->mt, 0, 0, 1, 0)) {
+ brw_end_of_pipe_sync(brw);
+ brw_render_cache_set_clear(brw);
+ }
} else {
intel_renderbuffer_downsample(brw, rb);
}
--
2.5.5
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