[Mesa-dev] [PATCH 00/10] i965/disasm: Shader disassembly formatting changes

Toni Lönnberg toni.lonnberg at intel.com
Mon Feb 20 13:27:40 UTC 2017

From: "Lonnberg, Toni" <toni.lonnberg at intel.com>

This and the previous shader disassembly patches replace these previous

[PATCH 3/3] Changed shader disassembler number formatting to use integers when the "disasm" debug flag is  used. Register types and regions are also now formatted more    like in the architecture documentation.
[PATCH 2/3] Added support for disassembling SENDS and SENDSC.
[PATCH 1/3] Added label support for shader disassembly. SEND and SENDC formatting now also includes the SFID information.

This patch set covers the formatting changes to the shader disassembly and the
introduction of the SENDS/SENDSC disassembly.

Lonnberg, Toni (10):
  i965/disasm: SFID and src1 decoding for SEND/SENDC instructions in
    shader disassembly
  i965/disasm: Instruction options field placement in shader disassembly
  i965/disasm: Formatting of decoded descriptors in SEND/SENDC
  i965/disasm: Support for disassembling SENDS and SENDSC
  i965/disasm: Register type formatting
  i965/disasm: Immediate value formatting
  i965/disasm: Immediate values as legible numbers
  i965/disasm: Register region formatting
  i965/disasm: Message descriptor type change
  i965/disasm: 3-src instruction swizzle output

 src/mesa/drivers/dri/i965/brw_disasm.c         | 329 ++++++++++++++++++-------
 src/mesa/drivers/dri/i965/brw_eu_emit.c        |   2 +-
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |   2 +-
 src/mesa/drivers/dri/i965/brw_inst.h           |  31 ++-
 4 files changed, 266 insertions(+), 98 deletions(-)


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