[Mesa-dev] [PATCH 12/24] radeonsi: set readnone on reads from read-only memory

Marek Olšák maraeo at gmail.com
Sat Feb 25 23:58:10 UTC 2017


From: Marek Olšák <marek.olsak at amd.com>

---
 src/amd/common/ac_llvm_build.c           | 11 +++++++++--
 src/amd/common/ac_llvm_build.h           |  3 ++-
 src/gallium/drivers/radeonsi/si_shader.c | 20 ++++++++++----------
 3 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 42965b6..f0ab9cb 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -612,21 +612,22 @@ ac_build_tbuffer_store_dwords(struct ac_llvm_context *ctx,
 
 LLVMValueRef
 ac_build_buffer_load(struct ac_llvm_context *ctx,
 		     LLVMValueRef rsrc,
 		     int num_channels,
 		     LLVMValueRef vindex,
 		     LLVMValueRef voffset,
 		     LLVMValueRef soffset,
 		     unsigned inst_offset,
 		     unsigned glc,
-		     unsigned slc)
+		     unsigned slc,
+		     bool readonly_memory)
 {
 	unsigned func = CLAMP(num_channels, 1, 3) - 1;
 
 	if (HAVE_LLVM >= 0x309) {
 		LLVMValueRef args[] = {
 			LLVMBuildBitCast(ctx->builder, rsrc, ctx->v4i32, ""),
 			vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
 			LLVMConstInt(ctx->i32, inst_offset, 0),
 			LLVMConstInt(ctx->i1, glc, 0),
 			LLVMConstInt(ctx->i1, slc, 0)
@@ -644,21 +645,27 @@ ac_build_buffer_load(struct ac_llvm_context *ctx,
 
 		if (soffset) {
 			args[2] = LLVMBuildAdd(ctx->builder, args[2], soffset,
 			                       "");
 		}
 
 		snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
 		         type_names[func]);
 
 		return ac_emit_llvm_intrinsic(ctx, name, types[func], args,
-					      ARRAY_SIZE(args), AC_FUNC_ATTR_READONLY);
+					      ARRAY_SIZE(args),
+					      /* READNONE means writes can't
+					       * affect it, while READONLY means
+					       * that writes can affect it. */
+					      readonly_memory ?
+						      AC_FUNC_ATTR_READNONE :
+						      AC_FUNC_ATTR_READONLY);
 	} else {
 		LLVMValueRef args[] = {
 			LLVMBuildBitCast(ctx->builder, rsrc, ctx->v16i8, ""),
 			voffset ? voffset : vindex,
 			soffset,
 			LLVMConstInt(ctx->i32, inst_offset, 0),
 			LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
 			LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
 			LLVMConstInt(ctx->i32, glc, 0),
 			LLVMConstInt(ctx->i32, slc, 0),
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index e6bb90f..e6e4e43 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -148,21 +148,22 @@ ac_build_tbuffer_store(struct ac_llvm_context *ctx,
 
 LLVMValueRef
 ac_build_buffer_load(struct ac_llvm_context *ctx,
 		     LLVMValueRef rsrc,
 		     int num_channels,
 		     LLVMValueRef vindex,
 		     LLVMValueRef voffset,
 		     LLVMValueRef soffset,
 		     unsigned inst_offset,
 		     unsigned glc,
-		     unsigned slc);
+		     unsigned slc,
+		     bool readonly_memory);
 
 LLVMValueRef
 ac_get_thread_id(struct ac_llvm_context *ctx);
 
 #define AC_TID_MASK_TOP_LEFT 0xfffffffc
 #define AC_TID_MASK_TOP      0xfffffffd
 #define AC_TID_MASK_LEFT     0xfffffffe
 
 LLVMValueRef
 ac_emit_ddxy(struct ac_llvm_context *ctx,
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 887e6a4..999aa40 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -819,49 +819,49 @@ static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
 	                           lp_build_const_int32(gallivm, param_index_base),
 	                           "");
 
 	return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
 					  vertex_index, param_index);
 }
 
 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
                                 enum tgsi_opcode_type type, unsigned swizzle,
                                 LLVMValueRef buffer, LLVMValueRef offset,
-                                LLVMValueRef base)
+                                LLVMValueRef base, bool readonly_memory)
 {
 	struct si_shader_context *ctx = si_shader_context(bld_base);
 	struct gallivm_state *gallivm = bld_base->base.gallivm;
 	LLVMValueRef value, value2;
 	LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
 	LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
 
 	if (swizzle == ~0) {
 		value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
-					     0, 1, 0);
+					     0, 1, 0, readonly_memory);
 
 		return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
 	}
 
 	if (!tgsi_type_is_64bit(type)) {
 		value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
-					     0, 1, 0);
+					     0, 1, 0, readonly_memory);
 
 		value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
 		return LLVMBuildExtractElement(gallivm->builder, value,
 		                    lp_build_const_int32(gallivm, swizzle), "");
 	}
 
 	value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
-	                          swizzle * 4, 1, 0);
+	                          swizzle * 4, 1, 0, readonly_memory);
 
 	value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
-	                           swizzle * 4 + 4, 1, 0);
+	                           swizzle * 4 + 4, 1, 0, readonly_memory);
 
 	return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
 }
 
 /**
  * Load from LDS.
  *
  * \param type		output value type
  * \param swizzle	offset (typically 0..3); it can be ~0, which loads a vec4
  * \param dw_addr	address in dwords
@@ -967,21 +967,21 @@ static LLVMValueRef fetch_input_tes(
 	LLVMValueRef rw_buffers, buffer, base, addr;
 
 	rw_buffers = LLVMGetParam(ctx->main_fn,
 				  SI_PARAM_RW_BUFFERS);
 	buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
 			lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
 
 	base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
 	addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
 
-	return buffer_load(bld_base, type, swizzle, buffer, base, addr);
+	return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
 }
 
 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
 			     const struct tgsi_full_instruction *inst,
 			     const struct tgsi_opcode_info *info,
 			     LLVMValueRef dst[4])
 {
 	struct si_shader_context *ctx = si_shader_context(bld_base);
 	struct gallivm_state *gallivm = bld_base->base.gallivm;
 	const struct tgsi_full_dst_register *reg = &inst->Dst[0];
@@ -1106,28 +1106,28 @@ static LLVMValueRef fetch_input_gs(
 	}
 	vtx_offset = lp_build_mul_imm(uint,
 				      LLVMGetParam(ctx->main_fn,
 						   vtx_offset_param),
 				      4);
 
 	param = si_shader_io_get_unique_index(semantic_name, semantic_index);
 	soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
 
 	value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, uint->zero,
-				     vtx_offset, soffset, 0, 1, 0);
+				     vtx_offset, soffset, 0, 1, 0, true);
 	if (tgsi_type_is_64bit(type)) {
 		LLVMValueRef value2;
 		soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
 
 		value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
 					      uint->zero, vtx_offset, soffset,
-					      0, 1, 0);
+					      0, 1, 0, true);
 		return si_llvm_emit_fetch_64bit(bld_base, type,
 						value, value2);
 	}
 	return LLVMBuildBitCast(gallivm->builder,
 				value,
 				tgsi2llvmtype(bld_base, type), "");
 }
 
 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
 {
@@ -1523,21 +1523,21 @@ static void declare_system_value(
 		rw_buffers = LLVMGetParam(ctx->main_fn,
 					SI_PARAM_RW_BUFFERS);
 		buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
 		        lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
 
 		base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
 		addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
 		                          lp_build_const_int32(gallivm, param));
 
 		value = buffer_load(&radeon_bld->bld_base, TGSI_TYPE_FLOAT,
-		                    ~0, buffer, base, addr);
+		                    ~0, buffer, base, addr, true);
 
 		break;
 	}
 
 	case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
 	case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
 	{
 		LLVMValueRef buf, slot, val[4];
 		int i, offset;
 
@@ -6211,21 +6211,21 @@ si_generate_gs_copy_shader(struct si_screen *sscreen,
 				}
 
 				LLVMValueRef soffset = LLVMConstInt(ctx.i32,
 					offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
 				offset++;
 
 				outputs[i].values[chan] =
 					ac_build_buffer_load(&ctx.ac,
 							     ctx.gsvs_ring[0], 1,
 							     uint->zero, voffset,
-							     soffset, 0, 1, 1);
+							     soffset, 0, 1, 1, true);
 			}
 		}
 
 		/* Streamout and exports. */
 		if (gs_selector->so.num_outputs) {
 			si_llvm_emit_streamout(&ctx, outputs,
 					       gsinfo->num_outputs,
 					       stream);
 		}
 
-- 
2.7.4



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