[Mesa-dev] [PATCH 1/2] i965: Replace bool aux disable with enum
Ben Widawsky
ben at bwidawsk.net
Mon Jan 2 01:02:36 UTC 2017
As CCS buffers are passed to KMS, it becomes useful to be able to
determine exactly what type of aux buffers are disabled. This was
previously not entirely needed (though the code was a little more
confusing), however it becomes very desirable after a recent patch from
Chad:
commit 1c8be049bea786c2c054a770025976beba5b8636
Author: Chad Versace <chadversary at chromium.org>
Date: Fri Dec 9 16:18:11 2016 -0800
i965/mt: Disable aux surfaces after making miptree shareable
The next patch will handle CCS and get rid of no_ccs.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 24 ++++++++++++------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 10 +++++++++-
2 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 11ad31d761..e99d8a128b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -64,7 +64,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
*/
static enum intel_msaa_layout
compute_msaa_layout(struct brw_context *brw, mesa_format format,
- bool disable_aux_buffers)
+ enum intel_aux_disable aux_disable)
{
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
if (brw->gen < 7)
@@ -90,7 +90,7 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format,
*/
if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT) {
return INTEL_MSAA_LAYOUT_UMS;
- } else if (disable_aux_buffers) {
+ } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
/* We can't use the CMS layout because it uses an aux buffer, the MCS
* buffer. So fallback to UMS, which is identical to CMS without the
* MCS. */
@@ -149,7 +149,7 @@ intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
if (brw->gen < 7)
return false;
- if (mt->disable_aux_buffers)
+ if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
return false;
/* This function applies only to non-multisampled render targets. */
@@ -322,7 +322,8 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->logical_width0 = width0;
mt->logical_height0 = height0;
mt->logical_depth0 = depth0;
- mt->disable_aux_buffers = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0;
+ mt->aux_disable = (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) != 0 ?
+ INTEL_AUX_DISABLE_ALL : INTEL_AUX_DISABLE_NONE;
mt->no_ccs = true;
mt->is_scanout = (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT) != 0;
exec_list_make_empty(&mt->hiz_map);
@@ -336,8 +337,7 @@ intel_miptree_create_layout(struct brw_context *brw,
int depth_multiply = 1;
if (num_samples > 1) {
/* Adjust width/height/depth for MSAA */
- mt->msaa_layout = compute_msaa_layout(brw, format,
- mt->disable_aux_buffers);
+ mt->msaa_layout = compute_msaa_layout(brw, format, mt->aux_disable);
if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
/* From the Ivybridge PRM, Volume 1, Part 1, page 108:
* "If the surface is multisampled and it is a depth or stencil
@@ -528,7 +528,7 @@ intel_miptree_create_layout(struct brw_context *brw,
brw_miptree_layout(brw, mt, layout_flags);
- if (mt->disable_aux_buffers)
+ if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
return mt;
@@ -1524,7 +1524,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
{
assert(brw->gen >= 7); /* MCS only used on Gen7+ */
assert(mt->mcs_buf == NULL);
- assert(!mt->disable_aux_buffers);
+ assert((mt->aux_disable & INTEL_AUX_DISABLE_MCS) == 0);
/* Choose the correct format for the MCS buffer. All that really matters
* is that we allocate the right buffer size, since we'll always be
@@ -1583,7 +1583,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
bool is_lossless_compressed)
{
assert(mt->mcs_buf == NULL);
- assert(!mt->disable_aux_buffers);
+ assert((mt->aux_disable & INTEL_AUX_DISABLE_MCS) == 0);
assert(!mt->no_ccs);
struct isl_surf temp_main_surf;
@@ -1922,7 +1922,7 @@ intel_miptree_wants_hiz_buffer(struct brw_context *brw,
if (mt->hiz_buf != NULL)
return false;
- if (mt->disable_aux_buffers)
+ if (mt->aux_disable & INTEL_AUX_DISABLE_HIZ)
return false;
switch (mt->format) {
@@ -1942,7 +1942,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
assert(mt->hiz_buf == NULL);
- assert(!mt->disable_aux_buffers);
+ assert((mt->aux_disable & INTEL_AUX_DISABLE_HIZ) == 0);
if (brw->gen == 7) {
mt->hiz_buf = intel_gen7_hiz_buf_create(brw, mt);
@@ -2346,7 +2346,7 @@ intel_miptree_make_shareable(struct brw_context *brw,
mt->hiz_buf = NULL;
}
- mt->disable_aux_buffers = true;
+ mt->aux_disable = INTEL_AUX_DISABLE_ALL;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index c67b4de8fa..896f35e0a1 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -253,6 +253,14 @@ enum miptree_array_layout {
ALL_SLICES_AT_EACH_LOD,
};
+enum intel_aux_disable {
+ INTEL_AUX_DISABLE_NONE = 0,
+ INTEL_AUX_DISABLE_HIZ = 1<<1,
+ INTEL_AUX_DISABLE_MCS = 1<<2,
+ INTEL_AUX_DISABLE_ALL = INTEL_AUX_DISABLE_HIZ |
+ INTEL_AUX_DISABLE_MCS
+};
+
/**
* Miptree aux buffer. These buffers are associated with a miptree, but the
* format is managed by the hardware.
@@ -638,7 +646,7 @@ struct intel_mipmap_tree
* buffer. This is useful for sharing the miptree bo with an external client
* that doesn't understand auxiliary buffers.
*/
- bool disable_aux_buffers;
+ enum intel_aux_disable aux_disable;
/**
* Fast clear and lossless compression are always disabled for this
--
2.11.0
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