[Mesa-dev] [PATCH 6/6] i965/gen7: Enable OpenGL 4.0 in Haswell when supported

[Iago Toral Quiroga]

---
 src/mesa/drivers/dri/i965/intel_extensions.c |  2 ++
 src/mesa/drivers/dri/i965/intel_screen.c     | 11 ++++++++---
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index 5be8f3a..6d9c370 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -204,6 +204,8 @@ intelInitExtensions(struct gl_context *ctx)
 
    if (brw->gen >= 8)
       ctx->Const.GLSLVersion = 450;
+   else if (brw->is_haswell && brw->can_do_pipelined_register_writes)
+      ctx->Const.GLSLVersion = 400;
    else if (brw->gen >= 6)
       ctx->Const.GLSLVersion = 330;
    else
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index d0e3ac6..d484b5d 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1434,7 +1434,8 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
 }
 
 static void
-set_max_gl_versions(struct intel_screen *screen)
+set_max_gl_versions(struct intel_screen *screen,
+                    bool can_do_pipelined_register_writes)
 {
    __DRIscreen *dri_screen = screen->driScrnPriv;
    const bool has_astc = screen->devinfo.gen >= 9;
@@ -1448,7 +1449,8 @@ set_max_gl_versions(struct intel_screen *screen)
       dri_screen->max_gl_es2_version = has_astc ? 32 : 31;
       break;
    case 7:
-      dri_screen->max_gl_core_version = 33;
+      dri_screen->max_gl_core_version = screen->devinfo.is_haswell &&
+         can_do_pipelined_register_writes ? 40 : 33;
       dri_screen->max_gl_compat_version = 30;
       dri_screen->max_gl_es1_version = 11;
       dri_screen->max_gl_es2_version = screen->devinfo.is_haswell ? 31 : 30;
@@ -1653,7 +1655,10 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
       screen->winsys_msaa_samples_override = -1;
    }
 
-   set_max_gl_versions(screen);
+   bool can_do_pipelined_register_writes =
+         brw_can_do_pipelined_register_writes(dri_screen);
+
+   set_max_gl_versions(screen, can_do_pipelined_register_writes);
 
    /* Notification of GPU resets requires hardware contexts and a kernel new
     * enough to support DRM_IOCTL_I915_GET_RESET_STATS.  If the ioctl is
-- 
2.7.4