[Mesa-dev] [PATCH v2 0/4] Enable OpenGL 4.0 on Haswell

[Iago Toral Quiroga]

Changes from v1:

- Use Chris's patch to check if we can do pipelined register writes instead
  of trying to reuse the infrastructure from intel_batchbuffer
- Add a kernel_features bitfield to the intel screen that we can check to
  see if specific features are available. Drop can_do_pipelined_register_writes
  from brw_context in favour of this bitfeld and rewrite the command parser
  version checks scattered through various places to read from this bitfield
  instead.

Ken, I decided to merge the check for CS_GPR and LOAD_REGISTER_REG into a
single feature flag, since that is how we current were doing this and we save
one flag, let me know if you prefer them to be separate flags.

Chris Wilson (1):
  i965: Move the pipelined test for SO register access to the screen

Iago Toral Quiroga (3):
  i965: get rid of brw->can_do_pipelined_register_writes
  i965/gen7: Enable OpenGL 4.0 in Haswell when supported
  i965: add a kernel_features bitfield to intel screen

 src/mesa/drivers/dri/i965/brw_context.c      |   4 +-
 src/mesa/drivers/dri/i965/brw_context.h      |   5 --
 src/mesa/drivers/dri/i965/gen7_l3_state.c    |   7 +-
 src/mesa/drivers/dri/i965/intel_extensions.c |  83 ++-----------------
 src/mesa/drivers/dri/i965/intel_screen.c     | 115 ++++++++++++++++++++++++++-
 src/mesa/drivers/dri/i965/intel_screen.h     |  45 +++++++++--
 6 files changed, 163 insertions(+), 96 deletions(-)

-- 
2.7.4