[Mesa-dev] [PATCH 1/2] vec4: use DIM instruction when loading DF immediates in HSW

[Matt Turner]

On Wed, Jan 4, 2017 at 6:36 AM, Samuel Iglesias Gonsálvez
<siglesias at igalia.com> wrote:
> On Tue, 2017-01-03 at 12:14 -0500, Matt Turner wrote:
>> On Tue, Jan 3, 2017 at 7:27 AM, Samuel Iglesias Gonsálvez
>> <siglesias at igalia.com> wrote:
>> > Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
>> > ---
>> >  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 9 +++++++++
>> >  1 file changed, 9 insertions(+)
>> >
>> > diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
>> > b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
>> > index 065e317..98e023a 100644
>> > --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
>> > +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
>> > @@ -1208,6 +1208,15 @@ vec4_visitor::setup_imm_df(double v)
>> >     if (devinfo->gen >= 8)
>> >        return brw_imm_df(v);
>> >
>> > +   /* gen7.5 does not support DF immediates straighforward but the
>> > DIM
>> > +    * instruction allows to set the 64-bit immediate value.
>> > +    */
>> > +   if (devinfo->is_haswell) {
>> > +      dst_reg dst = retype(dst_reg(VGRF, alloc.allocate(2)),
>> > BRW_REGISTER_TYPE_DF);
>>
>> Does this need to be alloc.allocate(2)? Since we're just loading
>> 64-bits worth of data, shouldn't one register be fine?
>>
>> If that is indeed okay, then with that change:
>>
>> Reviewed-by: Matt Turner <mattst88 at gmail.com>
>>
>
> Good question :-) We still need allocate(2) because the instruction
> that has the value loaded by DIM as a source, will read 2 GRFs (one per
> each vertex) regardless the vertical stride. This is because of the
> gen7 instruction decompresion bug (more info here [0]).
>
> This DIM instruction with exec_size = 8 will later be split in two of
> exec_size = 4 where each one write to one GRF, so the aforementioned HW
> bug is not causing problems :-)

Okay, makes sense. Thanks!

Reviewed-by: Matt Turner <mattst88 at gmail.com>

> Sam
>
> [0] https://bugs.freedesktop.org/show_bug.cgi?id=92760#c82