[Mesa-dev] [PATCH v2 4/4] i965: add a kernel_features bitfield to intel screen

Kenneth Graunke kenneth at whitecape.org
Wed Jan 4 23:35:11 UTC 2017


On Wednesday, January 4, 2017 1:26:23 PM PST Iago Toral Quiroga wrote:
> We can use this to track various features that may or may not be supported
> by the hw / kernel. Currently, we usually do this by checking the generation
> and supported command parser versions in various places thoughtout the driver
> code. With this patch, we centralize all these checks in just once place at
> screen creation time, then we just query the bitfield wherever we need to
> check if a particular feature is supported.
> ---
>  src/mesa/drivers/dri/i965/brw_context.c      |  4 +--
>  src/mesa/drivers/dri/i965/gen7_l3_state.c    |  2 +-
>  src/mesa/drivers/dri/i965/intel_extensions.c |  6 ++--
>  src/mesa/drivers/dri/i965/intel_screen.c     | 21 ++++++++++---
>  src/mesa/drivers/dri/i965/intel_screen.h     | 45 ++++++++++++++++++++--------
>  5 files changed, 56 insertions(+), 22 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
> index 3f3da7d..032b5ec 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -468,7 +468,7 @@ brw_init_driver_functions(struct brw_context *brw,
>  
>     functions->NewTransformFeedback = brw_new_transform_feedback;
>     functions->DeleteTransformFeedback = brw_delete_transform_feedback;
> -   if (brw->screen->has_mi_math_and_lrr) {
> +   if (can_do_mi_math_and_lrr(brw->screen)) {
>        functions->BeginTransformFeedback = hsw_begin_transform_feedback;
>        functions->EndTransformFeedback = hsw_end_transform_feedback;
>        functions->PauseTransformFeedback = hsw_pause_transform_feedback;
> @@ -608,7 +608,7 @@ brw_initialize_context_constants(struct brw_context *brw)
>        BRW_MAX_SOL_BINDINGS / BRW_MAX_SOL_BUFFERS;
>  
>     ctx->Const.AlwaysUseGetTransformFeedbackVertexCount =
> -      !brw->screen->has_mi_math_and_lrr;
> +      !can_do_mi_math_and_lrr(brw->screen);
>  
>     int max_samples;
>     const int *msaa_modes = intel_supported_msaa_modes(brw->screen);
> diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> index 85f8e46..dce39c3 100644
> --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> @@ -175,7 +175,7 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
>  
>        ADVANCE_BATCH();
>  
> -      if (brw->is_haswell && brw->screen->cmd_parser_version >= 4) {
> +      if (can_do_hsw_l3_atomics(brw->screen)) {
>           /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
>            * them disabled to avoid crashing the system hard.
>            */
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
> index aa89380..22651de 100644
> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
> @@ -227,14 +227,14 @@ intelInitExtensions(struct gl_context *ctx)
>           ctx->Extensions.ARB_transform_feedback3 = true;
>           ctx->Extensions.ARB_transform_feedback_instanced = true;
>  
> -         if ((brw->gen >= 8 || brw->screen->cmd_parser_version >= 5) &&
> +         if (can_do_compute_dispatch(brw->screen) &&
>               ctx->Const.MaxComputeWorkGroupSize[0] >= 1024) {
>              ctx->Extensions.ARB_compute_shader = true;
>              ctx->Extensions.ARB_ES3_1_compatibility =
>                 brw->gen >= 8 || brw->is_haswell;
>           }
>  
> -         if (brw->screen->cmd_parser_version >= 2)
> +         if (can_do_predicate_writes(brw->screen))
>              brw->predicate.supported = true;
>        }
>     }
> @@ -248,7 +248,7 @@ intelInitExtensions(struct gl_context *ctx)
>        ctx->Extensions.ARB_robust_buffer_access_behavior = true;
>     }
>  
> -   if (brw->screen->has_mi_math_and_lrr) {
> +   if (can_do_mi_math_and_lrr(brw->screen)) {
>        ctx->Extensions.ARB_query_buffer_object = true;
>     }
>  
> diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
> index c3fd6f6..f454fbd 100644
> --- a/src/mesa/drivers/dri/i965/intel_screen.c
> +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> @@ -1735,7 +1735,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
>     }
>  
>     if (intel_detect_pipelined_so(screen))
> -      screen->hw_has_pipelined_register |= HW_HAS_PIPELINED_SOL_OFFSET;
> +      screen->kernel_features |= KERNEL_ALLOWS_SOL_OFFSET_WRITES;
>  
>     const char *force_msaa = getenv("INTEL_FORCE_MSAA");
>     if (force_msaa) {
> @@ -1773,13 +1773,26 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
>        screen->cmd_parser_version = 0;
>     }
>  
> +   /* Haswell requires command parser version 4 in order to have L3
> +    * atomic scratch1 and chicken3 bits
> +    */
> +   if (screen->devinfo.is_haswell && screen->cmd_parser_version >= 4) {
> +      screen->kernel_features |=
> +         KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3;
> +   }
> +
>     /* Haswell requires command parser version 6 in order to write to the
>      * MI_MATH GPR registers, and version 7 in order to use
>      * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
>      */
> -   screen->has_mi_math_and_lrr = screen->devinfo.gen >= 8 ||
> -                                      (screen->devinfo.is_haswell &&
> -                                       screen->cmd_parser_version >= 7);
> +   if (screen->devinfo.gen >= 8 ||
> +       (screen->devinfo.is_haswell && screen->cmd_parser_version >= 7)) {
> +      screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR;
> +   }
> +
> +   /* Gen7 needs at least command parser version 5 to support compute */
> +   if (screen->devinfo.gen >= 8 || screen->cmd_parser_version >= 5)
> +      screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH;
>  

You're missing code to set KERNEL_ALLOWS_PREDICATE_WRITES here.

With that fixed, the series is:
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
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