[Mesa-dev] [PATCH 00/22] i965 Ivybridge ARB_gpu_shader_fp64 / OpenGL 4.0

[Samuel Iglesias Gonsálvez]

Hi,

This series implements initial support for Ivybridge FP64 for both
align16 and align1 backends, and with that we can enable FP64 and
OpenGL 4.0 in Ivybridge. 

These patches are available in our repository for testing. You can clone
it using the following command:

$ git clone -b i965-fp64-gen7-ivb-scalar-vec4-rc1 https://github.com/Igalia/mesa.git

The only feature missing in this series would be register spilling of
64-bit data. With this series all existing FP64 tests in Piglit pass on
Ivybridge, except for ~40 tests that fail to spill registers (mostly
the same varying-packing tests that failed in the scalar backend
before Curro fixed the scalar spilling implementation for SIMD32).

The main differences between HSW [0] and IVB with respect to FP64
support are that both execution size and regioning parameters (vertical
stride, horizontal stride and width) are in terms of floats, so we need
to duplicate both regioning parameters and execution size in the
instructions to have what the HW expects. For example, this instruction
in HSW:

		mov(4)  r10.0<1>:df, r11<4;4;1>:df

would be in IVB:

		mov (8) r10.0<1>:df r11.0<8;8,1>:df

Regards,

Sam

[0] https://lists.freedesktop.org/archives/mesa-dev/2016-July/123685.html

Iago Toral Quiroga (2):
  i965/disasm: also print nibctrl in IVB for execsize=8
  i965/fs: double-precision execution does not use 2 channels per DF in
    IVB/VLV

Juan A. Suarez Romero (13):
  i965/fs: add helper to retrieve instruction data size
  i965/fs: duplicate regioning parameters and execsize for DF in IVB/VLV
  i965/fs: add lowering step to duplicate sources with stride 0.
  i965/fs: consider execsize can be duplicated in lower_simd_with
  i965/fs: fix dst stride in IVB/VLV type conversions
  i965/fs: fix lower SIMD width for IVB/VLV's MOVE_INDIRECT
  i965/fs: add lowering x2d step for IVB/VLV
  i965/vec4: keep original type when dealing with null registers
  i965/vec4: fix double_to_single() for IVB/VLV
  i965/vec4: fix SIMD-width lowering for double_to_single operation in
    IVB/VLV
  i965/vec4: consider subregister offset in live variables
  i965/vec4: fix register_coalesce() for partial writes
  i965/vec4: fix SIMD-with lowering for CMP/MOV instructions with
    conditional modifiers

Samuel Iglesias Gonsálvez (7):
  i965/fs: indirect addressing with doubles is not supported in IVB/VLV
  i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on
    IVB/VLV
  i965/vec4: split DF instructions and later duplicate its execsize in
    IVB/VLV
  i965/vec4: adapt setup_imm_df() to allow inserting instructions before
    another one
  i965: enable ARB_gpu_shader_fp64 for Ivybridge/Valleyview
  i965: enable OpenGL 4.0 to Ivybridge/Valleyview
  docs: mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as supported by
    i965/gen7+

 docs/features.txt                                  |   4 +-
 src/mesa/drivers/dri/i965/Makefile.sources         |   1 +
 src/mesa/drivers/dri/i965/brw_disasm.c             |   7 ++
 src/mesa/drivers/dri/i965/brw_fs.cpp               | 115 ++++++++++++++++++--
 src/mesa/drivers/dri/i965/brw_fs.h                 |   2 +
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp     | 110 ++++++++++++++++---
 src/mesa/drivers/dri/i965/brw_fs_lower_ivb_x2d.cpp |  80 ++++++++++++++
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp           |  11 +-
 src/mesa/drivers/dri/i965/brw_ir_fs.h              |   1 +
 src/mesa/drivers/dri/i965/brw_ir_vec4.h            |   1 +
 src/mesa/drivers/dri/i965/brw_vec4.cpp             | 118 +++++++++++++++++++--
 src/mesa/drivers/dri/i965/brw_vec4.h               |   2 +
 .../drivers/dri/i965/brw_vec4_copy_propagation.cpp |   3 +-
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp   |  42 +++++++-
 .../drivers/dri/i965/brw_vec4_live_variables.cpp   |  12 ++-
 .../drivers/dri/i965/brw_vec4_live_variables.h     |  10 +-
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp         |  21 +++-
 src/mesa/drivers/dri/i965/intel_extensions.c       |   7 +-
 src/mesa/drivers/dri/i965/intel_screen.c           |   2 +-
 19 files changed, 487 insertions(+), 62 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/brw_fs_lower_ivb_x2d.cpp

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2.9.3