[Mesa-dev] [PATCH 7/7] nvc0: enable FBFETCH with a special slot for color buffer 0

[Ilia Mirkin]

On Thu, Jan 5, 2017 at 12:22 PM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> Would be nice to test on Maxwell as well.

No ES 3.1 there (yet), so no tests. I probably should have just forced
it. Will do.

>
> More comments inline.
>
> Thanks.
>
>
> On 01/02/2017 07:01 AM, Ilia Mirkin wrote:
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> index fe18f47..0d1ca2d 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> @@ -118,7 +118,7 @@ NVC0LegalizeSSA::handleFTZ(Instruction *i)
>>  void
>>  NVC0LegalizeSSA::handleTEXLOD(TexInstruction *i)
>>  {
>> -   if (i->tex.target.isMS())
>> +   if (i->tex.levelZero)
>>        return;
>
>
> Why do you need that change? isMS() should return true for the
> TexInstruction you create in handleBFETCH().

Yeah, but it didn't back before I handled MS, but was still setting
levelZero. I think this is right, since when levelZero is set, there
is no LOD arg. Ultimately this doesn't fix anything here. I should
have broken it out into a separate change, but I'm lazy.

>
>>
>>     ImmediateValue lod;
>> @@ -748,7 +748,10 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
>>           i->setIndirectR(hnd);
>>           i->setIndirectS(NULL);
>>        } else if (i->tex.r == i->tex.s || i->op == OP_TXF) {
>> -         i->tex.r += prog->driver->io.texBindBase / 4;
>> +         if (i->tex.r == 0xffff)
>> +            i->tex.r = prog->driver->io.fbtexBindBase / 4;
>> +         else
>> +            i->tex.r += prog->driver->io.texBindBase / 4;
>>           i->tex.s  = 0; // only a single cX[] value possible here
>>        } else {
>>           Value *hnd = bld.getScratch();
>> @@ -804,6 +807,10 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
>>        Value *ticRel = i->getIndirectR();
>>        Value *tscRel = i->getIndirectS();
>>
>> +      if (i->tex.r == 0xffff) {
>> +         i->tex.r = i->tex.s = 0x10;
>> +      }
>
>
> Why 16?

Because I haven't tested on Fermi :) It should be the "system"
texture/sampler. Needs testing, this was more placeholder than
anything. The tex op acts differently between linked and unlinked tsc
mode. Blob runs it in linked, we run unlinked (because of how Gallium
is structured).

Cheers,

  -ilia