[Mesa-dev] [PATCH v3 6/7] i965: Add support for xfb overflow query on conditional render.

[Kenneth Graunke]

On Tuesday, December 13, 2016 2:50:58 PM PST Rafael Antognolli wrote:
> Enable the use of a transform feedback overflow query with
> glBeginConditionalRender. The render commands will only execute if the
> query is true (i.e. if there was an overflow).
> 
> Use ARB_conditional_render_inverted to change this behavior.
> 
> Signed-off-by: Rafael Antognolli <rafael.antognolli at intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_conditional_render.c | 111 +++++++++++++++++++--
>  1 file changed, 101 insertions(+), 10 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_conditional_render.c b/src/mesa/drivers/dri/i965/brw_conditional_render.c
> index 122a4ec..db2b722 100644
> --- a/src/mesa/drivers/dri/i965/brw_conditional_render.c
> +++ b/src/mesa/drivers/dri/i965/brw_conditional_render.c
> @@ -48,20 +48,83 @@ set_predicate_enable(struct brw_context *brw,
>  }
>  
>  static void
> -set_predicate_for_result(struct brw_context *brw,
> -                         struct brw_query_object *query,
> -                         bool inverted)
> +set_predicate_for_overflow_query(struct brw_context *brw,
> +                                 struct brw_query_object *query,
> +                                 int stream_start, int count)
>  {
> -   int load_op;
> +   /* R3 = R4 - R3; generated vertices
> +    * R1 = R2 - R1; written vertices
> +    * R1 = R3 - R1; there was an overflow on this stream
> +    * R0 = R0 | R1; accumulate whether there was any overflow
> +    */
> +   static const uint32_t maths[] = {
> +      MI_MATH_ALU2(LOAD, SRCA, R4),
> +      MI_MATH_ALU2(LOAD, SRCB, R3),
> +      MI_MATH_ALU0(SUB),
> +      MI_MATH_ALU2(STORE, R3, ACCU),
> +      MI_MATH_ALU2(LOAD, SRCA, R2),
> +      MI_MATH_ALU2(LOAD, SRCB, R1),
> +      MI_MATH_ALU0(SUB),
> +      MI_MATH_ALU2(STORE, R1, ACCU),
> +      MI_MATH_ALU2(LOAD, SRCA, R3),
> +      MI_MATH_ALU2(LOAD, SRCB, R1),
> +      MI_MATH_ALU0(SUB),
> +      MI_MATH_ALU2(STORE, R1, ACCU),
> +      MI_MATH_ALU2(LOAD, SRCA, R1),
> +      MI_MATH_ALU2(LOAD, SRCB, R0),
> +      MI_MATH_ALU0(OR),
> +      MI_MATH_ALU2(STORE, R0, ACCU),
> +   };

It looks like this duplicates all of the logic from
load_gen_written_data_to_regs and calc_overflow_for_stream from the
previous patch.  Can we reuse some of that?

More importantly, I don't think this will work unless MI_MATH and
MI_LOAD_REGISTER_REG work.  can_do_mi_math_and_lrr(brw->screen) will
check that for you.  MI_MATH only exists on Haswell+.

I think we need to fall back to CPU-side conditional rendering if
MI_MATH isn't available.
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