[Mesa-dev] [PATCH 06/11] anv: Emit 3DSTATE_HS/TE/DS packets.
Jason Ekstrand
jason at jlekstrand.net
Mon Jan 9 16:35:44 UTC 2017
On Sun, Jan 8, 2017 at 9:26 PM, Kenneth Graunke <kenneth at whitecape.org>
wrote:
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
> src/intel/vulkan/anv_private.h | 2 +
> src/intel/vulkan/genX_pipeline.c | 87 ++++++++++++++++++++++++++++++
> ++++++++++
> src/intel/vulkan/genX_state.c | 4 --
> 3 files changed, 89 insertions(+), 4 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_
> private.h
> index 9e3b72e77bd..47b9eb3e94d 100644
> --- a/src/intel/vulkan/anv_private.h
> +++ b/src/intel/vulkan/anv_private.h
> @@ -1476,6 +1476,8 @@ get_##prefix##_prog_data(struct anv_pipeline
> *pipeline) \
> }
>
> ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
> +ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
> +ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
> ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
> ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
> ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
> diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_
> pipeline.c
> index 9ff84cd2921..80b7c75a47c 100644
> --- a/src/intel/vulkan/genX_pipeline.c
> +++ b/src/intel/vulkan/genX_pipeline.c
> @@ -965,6 +965,92 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
> }
>
> static void
> +emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
> +{
> + if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) {
> + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_HS), hs);
> + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), te);
> + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_DS), ds);
> + return;
> + }
> +
> + const struct gen_device_info *devinfo = &pipeline->device->info;
> + const struct anv_shader_bin *tcs_bin =
> + pipeline->shaders[MESA_SHADER_TESS_CTRL];
> + const struct anv_shader_bin *tes_bin =
> + pipeline->shaders[MESA_SHADER_TESS_EVAL];
> +
> + const struct brw_tcs_prog_data *tcs_prog_data =
> get_tcs_prog_data(pipeline);
> + const struct brw_tes_prog_data *tes_prog_data =
> get_tes_prog_data(pipeline);
> +
> + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_HS), hs) {
> + hs.Enable = true;
>
Mind whacking the XML to rename this to "FunctionEnable" to match VS, GS,
and DS?
> + hs.StatisticsEnable = true;
> + hs.SamplerCount = get_sampler_count(tcs_bin);
> + hs.BindingTableEntryCount = get_binding_table_entry_count(tcs_bin);
> + hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
> + hs.InstanceCount = tcs_prog_data->instances - 1;
> + hs.KernelStartPointer = tcs_bin->kernel.offset;
> +
> + hs.PerThreadScratchSpace = get_scratch_space(tcs_bin);
> + hs.ScratchSpaceBasePointer =
> + get_scratch_address(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
>
When I went through and unified stuff across gens, I tried to put things in
more-or-less the same order in the different packets. Specifically,
enable
stats enable
kernel pointer
various other enables and bits of info
URB
scratch
I would prefer to try and be somewhat consistent there if it's ok with you.
> +
> + hs.IncludeVertexHandles = true;
> + hs.DispatchGRFStartRegisterForURBData =
> + tcs_prog_data->base.base.dispatch_grf_start_reg;
> + hs.VertexURBEntryReadLength = 0;
> + hs.VertexURBEntryReadOffset = 0;
> + }
> +
> + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), te) {
> + te.Partitioning = tes_prog_data->partitioning;
> + te.OutputTopology = tes_prog_data->output_topology;
> + te.TEDomain = tes_prog_data->domain;
> + te.TEEnable = true;
> + te.MaximumTessellationFactorOdd = 63.0;
> + te.MaximumTessellationFactorNotOdd = 64.0;
> + }
> +
> + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_DS), ds) {
> + ds.KernelStartPointer = tes_bin->kernel.offset;
> + ds.SamplerCount = get_sampler_count(tes_bin);
> + ds.BindingTableEntryCount = get_binding_table_entry_count(tes_bin);
> +
> + ds.PerThreadScratchSpace = get_scratch_space(tes_bin);
> + ds.ScratchSpaceBasePointer =
> + get_scratch_address(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
> +
> + ds.DispatchGRFStartRegisterForURBData =
> + tes_prog_data->base.base.dispatch_grf_start_reg;
> + ds.PatchURBEntryReadLength = tes_prog_data->base.urb_read_length;
> + ds.PatchURBEntryReadOffset = 0;
> + ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
> + ds.StatisticsEnable = true;
> +
> + ds.ComputeWCoordinateEnable =
> + tes_prog_data->domain == BRW_TESS_DOMAIN_TRI;
> + ds.FunctionEnable = true;
> +
> +#if GEN_GEN >= 8
> + ds.DispatchMode =
> + tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8 ?
> + DISPATCH_MODE_SIMD8_SINGLE_PATCH :
> + DISPATCH_MODE_SIMD4X2;
> +
> + ds.UserClipDistanceClipTestEnableBitmask =
> + tes_prog_data->base.clip_distance_mask;
> + ds.UserClipDistanceCullTestEnableBitmask =
> + tes_prog_data->base.cull_distance_mask;
> +
> + ds.VertexURBEntryOutputReadOffset = 1;
> + ds.VertexURBEntryOutputLength =
> + (tes_prog_data->base.vue_map.num_slots + 1) / 2 - 1;
> +#endif
> + }
> +}
> +
> +static void
> emit_3dstate_gs(struct anv_pipeline *pipeline)
> {
> const struct gen_device_info *devinfo = &pipeline->device->info;
> @@ -1315,6 +1401,7 @@ genX(graphics_pipeline_create)(
> #endif
>
> emit_3dstate_vs(pipeline);
> + emit_3dstate_hs_te_ds(pipeline);
> emit_3dstate_gs(pipeline);
> emit_3dstate_sbe(pipeline);
> emit_3dstate_wm(pipeline, subpass, pCreateInfo->pMultisampleState);
> diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
> index 0f621f9a275..fd8f8ac9ce0 100644
> --- a/src/intel/vulkan/genX_state.c
> +++ b/src/intel/vulkan/genX_state.c
> @@ -55,10 +55,6 @@ genX(init_device_state)(struct anv_device *device)
> anv_batch_emit(&batch, GENX(3DSTATE_VF_STATISTICS), vfs)
> vfs.StatisticsEnable = true;
>
> - anv_batch_emit(&batch, GENX(3DSTATE_HS), hs);
> - anv_batch_emit(&batch, GENX(3DSTATE_TE), ts);
> - anv_batch_emit(&batch, GENX(3DSTATE_DS), ds);
> -
> anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
>
> anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
> --
> 2.11.0
>
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