[Mesa-dev] [PATCH 03/51] i965: Only flush the batchbuffer if we need to zero the SO offsets

[Chris Wilson]

If we don't have pipelined register access (e.g. Haswell before kernel
v4.2), then we can only implement EXT_transform_feedback by reseting the
SO offsets *between* batches. However, if we do have pipelined access to
the SO registers on gen7, we can simply emit an inline reset of the SO
registers without a full batch flush.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_context.h      |  1 +
 src/mesa/drivers/dri/i965/gen7_sol_state.c   | 13 ++++++++++++-
 src/mesa/drivers/dri/i965/intel_extensions.c |  1 +
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index ff3f861a14..d14369a531 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -829,6 +829,7 @@ struct brw_context
    bool no_simd8;
    bool use_rep_send;
    bool use_resource_streamer;
+   bool has_pipelined_so;
 
    /**
     * Some versions of Gen hardware don't do centroid interpolation correctly
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index e6b79ed234..656135fbce 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -493,7 +493,7 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
    /* Reset the SO buffer offsets to 0. */
    if (brw->gen >= 8) {
       brw_obj->zero_offsets = true;
-   } else {
+   } else if (!brw->has_pipelined_so) {
       intel_batchbuffer_flush(brw);
       brw->batch.needs_sol_reset = true;
    }
@@ -509,6 +509,17 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
       brw_obj->prims_generated[i] = 0;
    }
 
+   /* Reset the SOL buffer offset registers. */
+   if (brw->gen == 7 && brw->has_pipelined_so) {
+      for (int i = 0; i < 4; i++) {
+         BEGIN_BATCH(3);
+         OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
+         OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
+         OUT_BATCH(0);
+         ADVANCE_BATCH();
+      }
+   }
+
    /* Store the starting value of the SO_NUM_PRIMS_WRITTEN counters. */
    gen7_save_primitives_written_counters(brw, brw_obj);
 
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index 915797a58a..eafb76cd60 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -222,6 +222,7 @@ intelInitExtensions(struct gl_context *ctx)
          ctx->Extensions.ARB_gpu_shader_fp64 = true;
 
       if (can_do_pipelined_register_writes(brw->screen)) {
+         brw->has_pipelined_so = true;
          ctx->Extensions.ARB_draw_indirect = true;
          ctx->Extensions.ARB_transform_feedback2 = true;
          ctx->Extensions.ARB_transform_feedback3 = true;
-- 
2.11.0