[Mesa-dev] [PATCH 23/51] i965: Move bufmgr from brw_context to brw_batch
Chris Wilson
chris at chris-wilson.co.uk
Tue Jan 10 21:23:46 UTC 2017
Since brw_batch will become the dominate interface for brw_bo, move the
pointer now to reduce later churn.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_batch.h | 2 ++
src/mesa/drivers/dri/i965/brw_binding_tables.c | 2 +-
src/mesa/drivers/dri/i965/brw_context.c | 9 ++++-----
src/mesa/drivers/dri/i965/brw_context.h | 6 ++----
src/mesa/drivers/dri/i965/brw_program.c | 6 +++---
src/mesa/drivers/dri/i965/brw_program_cache.c | 4 ++--
src/mesa/drivers/dri/i965/brw_queryobj.c | 16 ++++++++--------
src/mesa/drivers/dri/i965/gen6_queryobj.c | 2 +-
src/mesa/drivers/dri/i965/gen6_sol.c | 4 ++--
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 14 +++++++-------
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 6 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 +++++++-------
src/mesa/drivers/dri/i965/intel_upload.c | 2 +-
13 files changed, 43 insertions(+), 44 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h b/src/mesa/drivers/dri/i965/brw_batch.h
index 37041f488a..9df23e63d6 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -68,6 +68,8 @@ typedef struct brw_batch {
int reloc_count;
} saved;
+ dri_bufmgr *bufmgr;
+
/**
* Set of brw_bo* that have been rendered to within this batchbuffer
* and would need flushing before being used from another cache domain that
diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c
index ae7b30a064..942f3f99eb 100644
--- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
+++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
@@ -385,7 +385,7 @@ gen7_enable_hw_binding_tables(struct brw_context *brw)
* "A maximum of 16,383 Binding tables are allowed in any batch buffer"
*/
static const int max_size = 16383 * 4;
- brw->hw_bt_pool.bo = drm_intel_bo_alloc(brw->bufmgr, "hw_bt",
+ brw->hw_bt_pool.bo = drm_intel_bo_alloc(brw->batch.bufmgr, "hw_bt",
max_size, 64);
brw->hw_bt_pool.next_offset = 0;
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index f4826fe727..ba16004ca9 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -879,7 +879,7 @@ brw_process_driconf_options(struct brw_context *brw)
case DRI_CONF_BO_REUSE_DISABLED:
break;
case DRI_CONF_BO_REUSE_ALL:
- intel_bufmgr_gem_enable_reuse(brw->bufmgr);
+ intel_bufmgr_gem_enable_reuse(brw->screen->bufmgr);
break;
}
@@ -965,7 +965,6 @@ brwCreateContext(gl_api api,
driContextPriv->driverPrivate = brw;
brw->driContext = driContextPriv;
brw->screen = screen;
- brw->bufmgr = screen->bufmgr;
brw->gen = devinfo->gen;
brw->gt = devinfo->gt;
@@ -1063,7 +1062,7 @@ brwCreateContext(gl_api api,
intel_fbo_init(brw);
- intel_batchbuffer_init(&brw->batch, brw->bufmgr, brw->has_llc);
+ intel_batchbuffer_init(&brw->batch, screen->bufmgr, brw->has_llc);
if (brw->gen >= 6) {
/* Create a new hardware context. Using a hardware context means that
@@ -1073,7 +1072,7 @@ brwCreateContext(gl_api api,
* This is required for transform feedback buffer offsets, query objects,
* and also allows us to reduce how much state we have to emit.
*/
- brw->hw_ctx = drm_intel_gem_context_create(brw->bufmgr);
+ brw->hw_ctx = drm_intel_gem_context_create(brw->batch.bufmgr);
if (!brw->hw_ctx) {
fprintf(stderr, "Gen6+ requires Kernel 3.6 or later.\n");
@@ -1628,7 +1627,7 @@ intel_process_dri2_buffer(struct brw_context *brw,
buffer->cpp, buffer->pitch);
}
- bo = drm_intel_bo_gem_create_from_name(brw->bufmgr, buffer_name,
+ bo = drm_intel_bo_gem_create_from_name(brw->batch.bufmgr, buffer_name,
buffer->name);
if (!bo) {
fprintf(stderr,
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index ccc75e7718..bf41be55ed 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -692,7 +692,8 @@ struct brw_context
} vtbl;
- dri_bufmgr *bufmgr;
+ brw_batch batch;
+ bool no_batch_wrap;
drm_intel_context *hw_ctx;
@@ -708,9 +709,6 @@ struct brw_context
*/
uint32_t reset_count;
- brw_batch batch;
- bool no_batch_wrap;
-
struct {
brw_bo *bo;
uint32_t next_offset;
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 034ea4fa1e..d0f66daaa1 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -339,7 +339,7 @@ brw_get_scratch_bo(struct brw_context *brw,
}
if (!old_bo) {
- *scratch_bo = drm_intel_bo_alloc(brw->bufmgr, "scratch bo", size, 4096);
+ *scratch_bo = drm_intel_bo_alloc(brw->batch.bufmgr, "scratch bo", size, 4096);
}
}
@@ -359,7 +359,7 @@ brw_alloc_stage_scratch(struct brw_context *brw,
brw_bo_put(stage_state->scratch_bo);
stage_state->scratch_bo =
- drm_intel_bo_alloc(brw->bufmgr, "shader scratch space",
+ drm_intel_bo_alloc(brw->batch.bufmgr, "shader scratch space",
per_thread_size * thread_count, 4096);
}
}
@@ -389,7 +389,7 @@ brw_init_shader_time(struct brw_context *brw)
{
const int max_entries = 2048;
brw->shader_time.bo =
- drm_intel_bo_alloc(brw->bufmgr, "shader time",
+ drm_intel_bo_alloc(brw->batch.bufmgr, "shader time",
max_entries * SHADER_TIME_STRIDE * 3, 4096);
brw->shader_time.names = rzalloc_array(brw, const char *, max_entries);
brw->shader_time.ids = rzalloc_array(brw, int, max_entries);
diff --git a/src/mesa/drivers/dri/i965/brw_program_cache.c b/src/mesa/drivers/dri/i965/brw_program_cache.c
index fdbca8dbf2..d1a10a78c6 100644
--- a/src/mesa/drivers/dri/i965/brw_program_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_program_cache.c
@@ -172,7 +172,7 @@ brw_cache_new_bo(struct brw_cache *cache, uint32_t new_size)
struct brw_context *brw = cache->brw;
brw_bo *new_bo;
- new_bo = drm_intel_bo_alloc(brw->bufmgr, "program cache", new_size, 64);
+ new_bo = drm_intel_bo_alloc(brw->batch.bufmgr, "program cache", new_size, 64);
if (brw->has_llc)
drm_intel_gem_bo_map_unsynchronized(new_bo);
@@ -346,7 +346,7 @@ brw_init_caches(struct brw_context *brw)
cache->items =
calloc(cache->size, sizeof(struct brw_cache_item *));
- cache->bo = drm_intel_bo_alloc(brw->bufmgr, "program cache", 4096, 64);
+ cache->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "program cache", 4096, 64);
if (brw->has_llc)
drm_intel_gem_bo_map_unsynchronized(cache->bo);
}
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 186aa217cc..a55751c0d3 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -233,7 +233,7 @@ brw_begin_query(struct gl_context *ctx, struct gl_query_object *q)
* the system was doing other work, such as running other applications.
*/
brw_bo_put(query->bo);
- query->bo = drm_intel_bo_alloc(brw->bufmgr, "timer query", 4096, 4096);
+ query->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "timer query", 4096, 4096);
brw_write_timestamp(brw, query->bo, 0);
break;
@@ -391,7 +391,7 @@ ensure_bo_has_space(struct gl_context *ctx, struct brw_query_object *query)
brw_queryobj_get_results(ctx, query);
}
- query->bo = drm_intel_bo_alloc(brw->bufmgr, "query", 4096, 1);
+ query->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "query", 4096, 1);
query->last_index = 0;
}
}
@@ -477,7 +477,7 @@ brw_query_counter(struct gl_context *ctx, struct gl_query_object *q)
assert(q->Target == GL_TIMESTAMP);
brw_bo_put(query->bo);
- query->bo = drm_intel_bo_alloc(brw->bufmgr, "timestamp query", 4096, 4096);
+ query->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "timestamp query", 4096, 4096);
brw_write_timestamp(brw, query->bo, 0);
query->flushed = false;
@@ -491,19 +491,19 @@ brw_query_counter(struct gl_context *ctx, struct gl_query_object *q)
static uint64_t
brw_get_timestamp(struct gl_context *ctx)
{
- struct brw_context *brw = brw_context(ctx);
+ struct intel_screen *screen = brw_context(ctx)->screen;
uint64_t result = 0;
- switch (brw->screen->hw_has_timestamp) {
+ switch (screen->hw_has_timestamp) {
case 3: /* New kernel, always full 36bit accuracy */
- drm_intel_reg_read(brw->bufmgr, TIMESTAMP | 1, &result);
+ drm_intel_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
break;
case 2: /* 64bit kernel, result is left-shifted by 32bits, losing 4bits */
- drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &result);
+ drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &result);
result = result >> 32;
break;
case 1: /* 32bit kernel, result is 36bit wide but may be inaccurate! */
- drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &result);
+ drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &result);
break;
}
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index a2b22c9247..4191ae51b0 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -277,7 +277,7 @@ gen6_begin_query(struct gl_context *ctx, struct gl_query_object *q)
/* Since we're starting a new query, we need to throw away old results. */
brw_bo_put(query->bo);
- query->bo = drm_intel_bo_alloc(brw->bufmgr, "query results", 4096, 4096);
+ query->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "query results", 4096, 4096);
/* For ARB_query_buffer_object: The result is not available */
set_query_availability(brw, query, false);
diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c b/src/mesa/drivers/dri/i965/gen6_sol.c
index 6aa1dfb555..69153aed5f 100644
--- a/src/mesa/drivers/dri/i965/gen6_sol.c
+++ b/src/mesa/drivers/dri/i965/gen6_sol.c
@@ -195,9 +195,9 @@ brw_new_transform_feedback(struct gl_context *ctx, GLuint name)
_mesa_init_transform_feedback_object(&brw_obj->base, name);
brw_obj->offset_bo =
- drm_intel_bo_alloc(brw->bufmgr, "transform feedback offsets", 16, 64);
+ drm_intel_bo_alloc(brw->batch.bufmgr, "transform feedback offsets", 16, 64);
brw_obj->prim_count_bo =
- drm_intel_bo_alloc(brw->bufmgr, "xfb primitive counts", 4096, 64);
+ drm_intel_bo_alloc(brw->batch.bufmgr, "xfb primitive counts", 4096, 64);
return &brw_obj->base;
}
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index a967351381..35b6161fad 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -37,14 +37,15 @@
#include <i915_drm.h>
static void
-intel_batchbuffer_reset(struct brw_batch *batch, dri_bufmgr *bufmgr,
- bool has_llc);
+intel_batchbuffer_reset(struct brw_batch *batch, bool has_llc);
void
intel_batchbuffer_init(struct brw_batch *batch, dri_bufmgr *bufmgr,
bool has_llc)
{
- intel_batchbuffer_reset(batch, bufmgr, has_llc);
+ batch->bufmgr = bufmgr;
+
+ intel_batchbuffer_reset(batch, has_llc);
if (!has_llc) {
batch->cpu_map = malloc(BATCH_SZ);
@@ -54,15 +55,14 @@ intel_batchbuffer_init(struct brw_batch *batch, dri_bufmgr *bufmgr,
}
static void
-intel_batchbuffer_reset(struct brw_batch *batch, dri_bufmgr *bufmgr,
- bool has_llc)
+intel_batchbuffer_reset(struct brw_batch *batch, bool has_llc)
{
brw_bo_put(batch->last_bo);
batch->last_bo = batch->bo;
brw_batch_clear_dirty(batch);
- batch->bo = drm_intel_bo_alloc(bufmgr, "batchbuffer", BATCH_SZ, 4096);
+ batch->bo = drm_intel_bo_alloc(batch->bufmgr, "batchbuffer", BATCH_SZ, 4096);
if (has_llc) {
drm_intel_bo_map(batch->bo, true);
batch->map = batch->bo->virtual;
@@ -186,7 +186,7 @@ brw_new_batch(struct brw_context *brw)
{
/* Create a new batchbuffer and reset the associated state: */
drm_intel_gem_bo_clear_relocs(brw->batch.bo, 0);
- intel_batchbuffer_reset(&brw->batch, brw->bufmgr, brw->has_llc);
+ intel_batchbuffer_reset(&brw->batch, brw->has_llc);
/* If the kernel supports hardware contexts, then most hardware state is
* preserved between batches; we only need to re-emit state that is required
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index 5fb2a884df..b077a3d828 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -98,7 +98,7 @@ static void
alloc_buffer_object(struct brw_context *brw,
struct intel_buffer_object *intel_obj)
{
- intel_obj->buffer = drm_intel_bo_alloc(brw->bufmgr, "bufferobj",
+ intel_obj->buffer = drm_intel_bo_alloc(brw->batch.bufmgr, "bufferobj",
intel_obj->Base.Size, 64);
/* the buffer might be bound as a uniform buffer, need to update it
@@ -285,7 +285,7 @@ brw_buffer_subdata(struct gl_context *ctx,
intel_obj->gpu_active_start,
intel_obj->gpu_active_end);
brw_bo *temp_bo =
- drm_intel_bo_alloc(brw->bufmgr, "subdata temp", size, 64);
+ drm_intel_bo_alloc(brw->batch.bufmgr, "subdata temp", size, 64);
drm_intel_bo_subdata(temp_bo, 0, size, data);
@@ -422,7 +422,7 @@ brw_map_buffer_range(struct gl_context *ctx,
const unsigned alignment = ctx->Const.MinMapBufferAlignment;
intel_obj->map_extra[index] = (uintptr_t) offset % alignment;
- intel_obj->range_map_bo[index] = drm_intel_bo_alloc(brw->bufmgr,
+ intel_obj->range_map_bo[index] = drm_intel_bo_alloc(brw->batch.bufmgr,
"BO blit temp",
length +
intel_obj->map_extra[index],
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 95d7a82f20..abd9517260 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -649,18 +649,18 @@ miptree_create(struct brw_context *brw,
unsigned long size;
size = intel_get_yf_ys_bo_size(mt, &alignment, &pitch);
assert(size);
- mt->bo = drm_intel_bo_alloc_for_render(brw->bufmgr, "miptree",
+ mt->bo = drm_intel_bo_alloc_for_render(brw->batch.bufmgr, "miptree",
size, alignment);
} else {
if (format == MESA_FORMAT_S_UINT8) {
/* Align to size of W tile, 64x64. */
- mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ mt->bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "miptree",
ALIGN(mt->total_width, 64),
ALIGN(mt->total_height, 64),
mt->cpp, &mt->tiling, &pitch,
alloc_flags);
} else {
- mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ mt->bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "miptree",
mt->total_width, mt->total_height,
mt->cpp, &mt->tiling, &pitch,
alloc_flags);
@@ -705,7 +705,7 @@ intel_miptree_create(struct brw_context *brw,
mt->tiling = I915_TILING_X;
brw_bo_put(mt->bo);
- mt->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "miptree",
+ mt->bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "miptree",
mt->total_width, mt->total_height, mt->cpp,
&mt->tiling, &pitch, alloc_flags);
mt->pitch = pitch;
@@ -1618,7 +1618,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
* Therefore one can pass the ISL dimensions in terms of bytes instead of
* trying to recalculate based on different format block sizes.
*/
- buf->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "ccs-miptree",
+ buf->bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "ccs-miptree",
buf->pitch, buf->size / buf->pitch,
1, &tiling, &pitch, alloc_flags);
if (buf->bo) {
@@ -1755,7 +1755,7 @@ intel_gen7_hiz_buf_create(struct brw_context *brw,
unsigned long pitch;
uint32_t tiling = I915_TILING_Y;
- buf->aux_base.bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "hiz",
+ buf->aux_base.bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "hiz",
hz_width, hz_height, 1,
&tiling, &pitch,
BO_ALLOC_FOR_RENDER);
@@ -1852,7 +1852,7 @@ intel_gen8_hiz_buf_create(struct brw_context *brw,
unsigned long pitch;
uint32_t tiling = I915_TILING_Y;
- buf->aux_base.bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "hiz",
+ buf->aux_base.bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "hiz",
hz_width, hz_height, 1,
&tiling, &pitch,
BO_ALLOC_FOR_RENDER);
diff --git a/src/mesa/drivers/dri/i965/intel_upload.c b/src/mesa/drivers/dri/i965/intel_upload.c
index ab86439152..ce8edcb0b6 100644
--- a/src/mesa/drivers/dri/i965/intel_upload.c
+++ b/src/mesa/drivers/dri/i965/intel_upload.c
@@ -94,7 +94,7 @@ intel_upload_space(struct brw_context *brw,
}
if (!brw->upload.bo) {
- brw->upload.bo = drm_intel_bo_alloc(brw->bufmgr, "streamed data",
+ brw->upload.bo = drm_intel_bo_alloc(brw->batch.bufmgr, "streamed data",
MAX2(INTEL_UPLOAD_SIZE, size), 4096);
if (brw->has_llc)
drm_intel_bo_map(brw->upload.bo, true);
--
2.11.0
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