[Mesa-dev] [PATCH 21/51] i965: Refactor adding relocations into the batch buffer
Chris Wilson
chris at chris-wilson.co.uk
Tue Jan 10 21:23:44 UTC 2017
It is essential that the value we write into the batch buffer matches
the value we record in the relocation entry (and that value also
corresponds with the presumed offset the target buffer). To ensure this
is true we combine adding relocation entry to the batch buffer with
recording the target address into the state with a convenient helper.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_batch.h | 54 ++++++++++++++++++
src/mesa/drivers/dri/i965/brw_cc.c | 14 ++---
src/mesa/drivers/dri/i965/brw_clip_state.c | 14 ++---
src/mesa/drivers/dri/i965/brw_context.h | 10 +---
src/mesa/drivers/dri/i965/brw_sampler_state.c | 8 +--
src/mesa/drivers/dri/i965/brw_sf_state.c | 20 +++----
src/mesa/drivers/dri/i965/brw_vs_state.c | 55 +++++++-----------
src/mesa/drivers/dri/i965/brw_wm_state.c | 62 +++++++--------------
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 71 +++++++++---------------
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 26 +++------
10 files changed, 151 insertions(+), 183 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h b/src/mesa/drivers/dri/i965/brw_batch.h
index 09065cf972..37041f488a 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -108,6 +108,60 @@ inline static bool brw_batch_busy(brw_batch *batch)
return batch->last_bo && drm_intel_bo_busy(batch->last_bo);
}
+#define GEN8_HIGH_ADDRESS_BIT 47
+static uint64_t gen8_canonical_address(uint64_t address)
+{
+ const uint8_t shift = 63 - GEN8_HIGH_ADDRESS_BIT;
+ return (int64_t)(address << shift) >> shift;
+}
+
+inline static uint64_t
+__brw_reloc_address(brw_bo *bo, uint64_t offset)
+{
+ return gen8_canonical_address(bo->offset64 + offset);
+}
+
+inline static uint64_t
+brw_reloc_address(brw_bo *bo, uint64_t offset)
+{
+ return bo ? __brw_reloc_address(bo, offset) : 0;
+}
+
+inline static uint64_t
+__brw_batch_reloc(brw_batch *batch,
+ uint32_t batch_offset,
+ brw_bo *target_bo,
+ uint64_t target_offset,
+ unsigned read_domains,
+ unsigned write_domain)
+{
+ int ret;
+
+ ret = drm_intel_bo_emit_reloc(batch->bo, batch_offset,
+ target_bo, target_offset,
+ read_domains, write_domain);
+ assert(ret == 0);
+ (void)ret;
+
+ return __brw_reloc_address(target_bo, target_offset);
+}
+
+inline static uint64_t
+brw_batch_reloc(brw_batch *batch,
+ uint32_t batch_offset,
+ brw_bo *target_bo,
+ uint64_t target_offset,
+ unsigned read_domains,
+ unsigned write_domain)
+{
+ if (target_bo == NULL)
+ return 0;
+
+ return __brw_batch_reloc(batch, batch_offset,
+ target_bo, target_offset,
+ read_domains, write_domain);
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index 35bc73e65f..af095c5713 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -231,17 +231,13 @@ static void upload_cc_unit(struct brw_context *brw)
cc->cc5.statistics_enable = 1;
/* BRW_NEW_CC_VP */
- cc->cc4.cc_viewport_state_offset = (brw->batch.bo->offset64 +
- brw->cc.vp_offset) >> 5; /* reloc */
+ cc->dw4 = brw_batch_reloc(&brw->batch,
+ brw->cc.state_offset +
+ offsetof(struct brw_cc_unit_state, cc4),
+ brw->batch.bo, brw->cc.vp_offset,
+ I915_GEM_DOMAIN_INSTRUCTION, 0);
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
-
- /* Emit CC viewport relocation */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- (brw->cc.state_offset +
- offsetof(struct brw_cc_unit_state, cc4)),
- brw->batch.bo, brw->cc.vp_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
}
const struct brw_tracked_state brw_cc_unit = {
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 39c149c976..d933b0aebb 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -134,15 +134,11 @@ brw_upload_clip_unit(struct brw_context *brw)
ctx->ViewportArray[0].Height == fb_height)
{
clip->clip5.guard_band_enable = 1;
- clip->clip6.clipper_viewport_state_ptr =
- (brw->batch.bo->offset64 + brw->clip.vp_offset) >> 5;
-
- /* emit clip viewport relocation */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- (brw->clip.state_offset +
- offsetof(struct brw_clip_unit_state, clip6)),
- brw->batch.bo, brw->clip.vp_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
+ clip->dw6 = brw_batch_reloc(&brw->batch,
+ brw->clip.state_offset +
+ offsetof(struct brw_clip_unit_state, clip6),
+ brw->batch.bo, brw->clip.vp_offset,
+ I915_GEM_DOMAIN_INSTRUCTION, 0);
}
/* _NEW_TRANSFORM */
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index ff0e9d7c64..ccc75e7718 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1575,13 +1575,9 @@ brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
return prog_offset;
}
- drm_intel_bo_emit_reloc(brw->batch.bo,
- state_offset,
- brw->cache.bo,
- prog_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
-
- return brw->cache.bo->offset64 + prog_offset;
+ return brw_batch_reloc(&brw->batch, state_offset,
+ brw->cache.bo, prog_offset,
+ I915_GEM_DOMAIN_INSTRUCTION, 0);
}
bool brw_do_cubemap_normalize(struct exec_list *instructions);
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index 9cef97562d..e247ff66f1 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -100,14 +100,12 @@ brw_emit_sampler_state(struct brw_context *brw,
SET_FIELD(mag_filter, BRW_SAMPLER_MAG_FILTER) |
SET_FIELD(min_filter, BRW_SAMPLER_MIN_FILTER);
- ss[2] = border_color_offset;
if (brw->gen < 6) {
- ss[2] += brw->batch.bo->offset64; /* reloc */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- batch_offset_for_sampler_state + 8,
+ ss[2] = brw_batch_reloc(&brw->batch, batch_offset_for_sampler_state + 8,
brw->batch.bo, border_color_offset,
I915_GEM_DOMAIN_SAMPLER, 0);
- }
+ } else
+ ss[2] = border_color_offset;
ss[3] = SET_FIELD(max_anisotropy, BRW_SAMPLER_MAX_ANISOTROPY) |
SET_FIELD(address_rounding, BRW_SAMPLER_ADDRESS_ROUNDING);
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 6d1f1998b6..f8c4209d1d 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -134,7 +134,6 @@ static void upload_sf_unit( struct brw_context *brw )
{
struct gl_context *ctx = &brw->ctx;
struct brw_sf_unit_state *sf;
- brw_bo *bo = brw->batch.bo;
int chipset_max_threads;
bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
@@ -180,9 +179,6 @@ static void upload_sf_unit( struct brw_context *brw )
sf->thread4.stats_enable = 1;
/* BRW_NEW_SF_VP */
- sf->sf5.sf_viewport_state_offset = (brw->batch.bo->offset64 +
- brw->sf.vp_offset) >> 5; /* reloc */
-
sf->sf5.viewport_transform = 1;
/* _NEW_SCISSOR */
@@ -201,6 +197,14 @@ static void upload_sf_unit( struct brw_context *brw )
*/
sf->sf5.front_winding ^= render_to_fbo;
+ sf->dw5 = brw_batch_reloc(&brw->batch,
+ brw->sf.state_offset +
+ offsetof(struct brw_sf_unit_state, sf5),
+ brw->batch.bo,
+ brw->sf.vp_offset | sf->dw5,
+ I915_GEM_DOMAIN_INSTRUCTION, 0);
+
+
/* _NEW_POLYGON */
switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
case GL_FRONT:
@@ -292,14 +296,6 @@ static void upload_sf_unit( struct brw_context *brw )
* something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
*/
- /* Emit SF viewport relocation */
- drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
- offsetof(struct brw_sf_unit_state, sf5)),
- brw->batch.bo, (brw->sf.vp_offset |
- sf->sf5.front_winding |
- (sf->sf5.viewport_transform << 1)),
- I915_GEM_DOMAIN_INSTRUCTION, 0);
-
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index d0d2695a49..d4ef06fd1d 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -82,15 +82,13 @@ brw_upload_vs_unit(struct brw_context *brw)
vs->thread1.binding_table_entry_count =
prog_data->binding_table.size_bytes / 4;
- if (prog_data->total_scratch != 0) {
- vs->thread2.scratch_space_base_pointer =
- stage_state->scratch_bo->offset64 >> 10; /* reloc */
- vs->thread2.per_thread_scratch_space =
- ffs(stage_state->per_thread_scratch) - 11;
- } else {
- vs->thread2.scratch_space_base_pointer = 0;
- vs->thread2.per_thread_scratch_space = 0;
- }
+ if (prog_data->total_scratch != 0)
+ vs->dw2 = brw_batch_reloc(&brw->batch,
+ stage_state->state_offset +
+ offsetof(struct brw_vs_unit_state, thread2),
+ stage_state->scratch_bo,
+ ffs(stage_state->per_thread_scratch) - 11,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
vs->thread3.urb_entry_read_length = vue_prog_data->urb_read_length;
vs->thread3.const_urb_entry_read_length = prog_data->curb_read_length;
@@ -140,13 +138,6 @@ brw_upload_vs_unit(struct brw_context *brw)
vs->thread4.max_threads = CLAMP(brw->urb.nr_vs_entries / 2,
1, devinfo->max_vs_threads) - 1;
- if (brw->gen == 5)
- vs->vs5.sampler_count = 0; /* hardware requirement */
- else {
- vs->vs5.sampler_count = (stage_state->sampler_count + 3) / 4;
- }
-
-
if (unlikely(INTEL_DEBUG & DEBUG_STATS))
vs->thread4.stats_enable = 1;
@@ -157,26 +148,20 @@ brw_upload_vs_unit(struct brw_context *brw)
/* Set the sampler state pointer, and its reloc
*/
if (stage_state->sampler_count) {
- /* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
- vs->vs5.sampler_state_pointer =
- (brw->batch.bo->offset64 + stage_state->sampler_offset) >> 5;
- drm_intel_bo_emit_reloc(brw->batch.bo,
- stage_state->state_offset +
- offsetof(struct brw_vs_unit_state, vs5),
- brw->batch.bo,
- (stage_state->sampler_offset |
- vs->vs5.sampler_count),
- I915_GEM_DOMAIN_INSTRUCTION, 0);
- }
+ int sampler_count;
- /* Emit scratch space relocation */
- if (prog_data->total_scratch != 0) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
- stage_state->state_offset +
- offsetof(struct brw_vs_unit_state, thread2),
- stage_state->scratch_bo,
- vs->thread2.per_thread_scratch_space,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ if (brw->gen == 5)
+ sampler_count = 0; /* hardware requirement */
+ else
+ sampler_count = (brw->wm.base.sampler_count + 1) / 4;
+
+ /* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
+ vs->dw5 = brw_batch_reloc(&brw->batch,
+ stage_state->state_offset +
+ offsetof(struct brw_vs_unit_state, vs5),
+ brw->batch.bo,
+ stage_state->sampler_offset | sampler_count,
+ I915_GEM_DOMAIN_INSTRUCTION, 0);
}
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index bf32ac9396..5054674db5 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -131,15 +131,13 @@ brw_upload_wm_unit(struct brw_context *brw)
wm->thread1.binding_table_entry_count =
prog_data->base.binding_table.size_bytes / 4;
- if (prog_data->base.total_scratch != 0) {
- wm->thread2.scratch_space_base_pointer =
- brw->wm.base.scratch_bo->offset64 >> 10; /* reloc */
- wm->thread2.per_thread_scratch_space =
- ffs(brw->wm.base.per_thread_scratch) - 11;
- } else {
- wm->thread2.scratch_space_base_pointer = 0;
- wm->thread2.per_thread_scratch_space = 0;
- }
+ if (prog_data->base.total_scratch != 0)
+ wm->dw2 = brw_batch_reloc(&brw->batch,
+ brw->wm.base.state_offset +
+ offsetof(struct brw_wm_unit_state, thread2),
+ brw->wm.base.scratch_bo,
+ ffs(brw->wm.base.per_thread_scratch) - 11,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
wm->thread3.dispatch_grf_start_reg =
prog_data->base.dispatch_grf_start_reg;
@@ -151,18 +149,21 @@ brw_upload_wm_unit(struct brw_context *brw)
/* BRW_NEW_CURBE_OFFSETS */
wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
- if (brw->gen == 5)
- wm->wm4.sampler_count = 0; /* hardware requirement */
- else {
- wm->wm4.sampler_count = (brw->wm.base.sampler_count + 1) / 4;
- }
+ if (unlikely(INTEL_DEBUG & DEBUG_STATS) || brw->stats_wm)
+ wm->wm4.stats_enable = 1;
+ /* BRW_NEW_STATS_WM */
if (brw->wm.base.sampler_count) {
+ if (brw->gen != 5) /* hardware requirement */
+ wm->wm4.sampler_count = (brw->wm.base.sampler_count + 1) / 4;
+
/* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
- wm->wm4.sampler_state_pointer = (brw->batch.bo->offset64 +
- brw->wm.base.sampler_offset) >> 5;
- } else {
- wm->wm4.sampler_state_pointer = 0;
+ wm->dw4 = brw_batch_reloc(&brw->batch,
+ brw->wm.base.state_offset +
+ offsetof(struct brw_wm_unit_state, wm4),
+ brw->batch.bo,
+ brw->wm.base.sampler_offset | wm->dw4,
+ I915_GEM_DOMAIN_INSTRUCTION, 0);
}
/* BRW_NEW_FRAGMENT_PROGRAM */
@@ -216,31 +217,6 @@ brw_upload_wm_unit(struct brw_context *brw)
/* _NEW_LINE */
wm->wm5.line_stipple = ctx->Line.StippleFlag;
- /* BRW_NEW_STATS_WM */
- if (unlikely(INTEL_DEBUG & DEBUG_STATS) || brw->stats_wm)
- wm->wm4.stats_enable = 1;
-
- /* Emit scratch space relocation */
- if (prog_data->base.total_scratch != 0) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.state_offset +
- offsetof(struct brw_wm_unit_state, thread2),
- brw->wm.base.scratch_bo,
- wm->thread2.per_thread_scratch_space,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
- }
-
- /* Emit sampler state relocation */
- if (brw->wm.base.sampler_count != 0) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.state_offset +
- offsetof(struct brw_wm_unit_state, wm4),
- brw->batch.bo, (brw->wm.base.sampler_offset |
- wm->wm4.stats_enable |
- (wm->wm4.sampler_count << 2)),
- I915_GEM_DOMAIN_INSTRUCTION, 0);
- }
-
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
/* _NEW_POLGYON */
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c93d11bf88..6a7f88dcee 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -144,10 +144,10 @@ brw_emit_surface_state(struct brw_context *brw,
if (mt->mcs_buf) {
assert(mt->mcs_buf->offset == 0);
aux_bo = mt->mcs_buf->bo;
- aux_offset = mt->mcs_buf->bo->offset64 + mt->mcs_buf->offset;
+ aux_offset = brw_reloc_address(mt->mcs_buf->bo, mt->mcs_buf->offset);
} else {
aux_bo = mt->hiz_buf->aux_base.bo;
- aux_offset = mt->hiz_buf->aux_base.bo->offset64;
+ aux_offset = brw_reloc_address(mt->hiz_buf->aux_base.bo, 0);
}
/* We only really need a clear color if we also have an auxiliary
@@ -162,17 +162,15 @@ brw_emit_surface_state(struct brw_context *brw,
surf_index, surf_offset);
isl_surf_fill_state(&brw->isl_dev, state, .surf = &surf, .view = &view,
- .address = mt->bo->offset64 + offset,
+ .address = brw_batch_reloc(&brw->batch,
+ *surf_offset + brw->isl_dev.ss.addr_offset,
+ mt->bo, offset,
+ read_domains, write_domains),
.aux_surf = aux_surf, .aux_usage = aux_usage,
.aux_address = aux_offset,
.mocs = mocs, .clear_color = clear_color,
.x_offset_sa = tile_x, .y_offset_sa = tile_y);
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + brw->isl_dev.ss.addr_offset,
- mt->bo, offset,
- read_domains, write_domains);
-
if (aux_surf) {
/* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the
* upper 20 bits of the GPU address of the MCS buffer; the lower 12 bits
@@ -182,10 +180,10 @@ brw_emit_surface_state(struct brw_context *brw,
*/
assert((aux_offset & 0xfff) == 0);
uint32_t *aux_addr = state + brw->isl_dev.ss.aux_addr_offset;
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + brw->isl_dev.ss.aux_addr_offset,
- aux_bo, *aux_addr & 0xfff,
- read_domains, write_domains);
+ brw_batch_reloc(&brw->batch,
+ *surf_offset + brw->isl_dev.ss.aux_addr_offset,
+ aux_bo, *aux_addr & 0xfff,
+ read_domains, write_domains);
}
}
@@ -659,19 +657,15 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
out_offset);
isl_buffer_fill_state(&brw->isl_dev, dw,
- .address = (bo ? bo->offset64 : 0) + buffer_offset,
+ .address = brw_batch_reloc(&brw->batch,
+ *out_offset + brw->isl_dev.ss.addr_offset,
+ bo, buffer_offset,
+ I915_GEM_DOMAIN_SAMPLER,
+ (rw ? I915_GEM_DOMAIN_SAMPLER : 0)),
.size = buffer_size,
.format = surface_format,
.stride = pitch,
.mocs = tex_mocs[brw->gen]);
-
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *out_offset + brw->isl_dev.ss.addr_offset,
- bo, buffer_offset,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
- }
}
void
@@ -815,19 +809,15 @@ brw_update_sol_surface(struct brw_context *brw,
BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
BRW_SURFACE_RC_READ_WRITE;
- surf[1] = bo->offset64 + offset_bytes; /* reloc */
+ surf[1] = brw_batch_reloc(&brw->batch, *out_offset + 4,
+ bo, offset_bytes,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
height << BRW_SURFACE_HEIGHT_SHIFT);
surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
surf[4] = 0;
surf[5] = 0;
-
- /* Emit relocation to surface contents. */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *out_offset + 4,
- bo, offset_bytes,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
}
/* Creates a new WM constant buffer reflecting the current fragment program's
@@ -936,7 +926,9 @@ brw_emit_null_surface_state(struct brw_context *brw,
1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT |
1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
}
- surf[1] = bo ? bo->offset64 : 0;
+ surf[1] = brw_batch_reloc(&brw->batch, *out_offset + 4,
+ bo, 0,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
surf[2] = ((width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
@@ -949,13 +941,6 @@ brw_emit_null_surface_state(struct brw_context *brw,
pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT);
surf[4] = multisampling_state;
surf[5] = 0;
-
- if (bo) {
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *out_offset + 4,
- bo, 0,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
- }
}
/**
@@ -1011,8 +996,11 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
/* reloc */
assert(mt->offset % mt->cpp == 0);
- surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
- mt->bo->offset64 + mt->offset);
+ surf[1] = brw_batch_reloc(&brw->batch, offset + 4,
+ mt->bo,
+ mt->offset +
+ intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y),
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
@@ -1054,13 +1042,6 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
}
}
- drm_intel_bo_emit_reloc(brw->batch.bo,
- offset + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
-
return offset;
}
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 2e6ee0cb8b..997bc2fa24 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -51,19 +51,10 @@ blorp_emit_reloc(struct blorp_batch *batch,
{
assert(batch->blorp->driver_ctx == batch->driver_batch);
struct brw_context *brw = batch->driver_batch;
-
- uint32_t offset = (char *)location - (char *)brw->batch.map;
- if (brw->gen >= 8) {
- return intel_batchbuffer_reloc64(&brw->batch, address.buffer, offset,
- address.read_domains,
- address.write_domain,
- address.offset + delta);
- } else {
- return intel_batchbuffer_reloc(&brw->batch, address.buffer, offset,
- address.read_domains,
- address.write_domain,
- address.offset + delta);
- }
+ return __brw_batch_reloc(&brw->batch,
+ (char *)location - (char *)brw->batch.map,
+ address.buffer, address.offset + delta,
+ address.read_domains, address.write_domain);
}
static void
@@ -72,13 +63,12 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
{
assert(batch->blorp->driver_ctx == batch->driver_batch);
struct brw_context *brw = batch->driver_batch;
- brw_bo *bo = address.buffer;
- drm_intel_bo_emit_reloc(brw->batch.bo, ss_offset,
- bo, address.offset + delta,
- address.read_domains, address.write_domain);
+ uint64_t reloc_val =
+ __brw_batch_reloc(&brw->batch, ss_offset,
+ address.buffer, address.offset + delta,
+ address.read_domains, address.write_domain);
- uint64_t reloc_val = bo->offset64 + address.offset + delta;
void *reloc_ptr = (void *)brw->batch.map + ss_offset;
#if GEN_GEN >= 8
*(uint64_t *)reloc_ptr = reloc_val;
--
2.11.0
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