[Mesa-dev] [PATCH 27/51] i965: Move brw_bo creation to brw_batch.h
Chris Wilson
chris at chris-wilson.co.uk
Tue Jan 10 21:23:50 UTC 2017
Churn now to reduce churn later.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_batch.h | 34 +++++++++++++
src/mesa/drivers/dri/i965/brw_binding_tables.c | 3 +-
src/mesa/drivers/dri/i965/brw_context.c | 3 +-
src/mesa/drivers/dri/i965/brw_program.c | 13 ++---
src/mesa/drivers/dri/i965/brw_program_cache.c | 4 +-
src/mesa/drivers/dri/i965/brw_queryobj.c | 6 +--
src/mesa/drivers/dri/i965/gen6_queryobj.c | 2 +-
src/mesa/drivers/dri/i965/gen6_sol.c | 4 +-
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 +-
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 16 +++----
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 61 +++++++++++-------------
src/mesa/drivers/dri/i965/intel_upload.c | 4 +-
12 files changed, 91 insertions(+), 61 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h b/src/mesa/drivers/dri/i965/brw_batch.h
index 38d83bc92b..f2422b8f39 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -100,6 +100,40 @@ typedef struct brw_batch {
struct set *render_cache;
} brw_batch;
+inline static brw_bo *brw_bo_create(brw_batch *batch,
+ const char *name,
+ uint64_t size,
+ uint64_t alignment,
+ unsigned flags)
+{
+ return drm_intel_bo_alloc(batch->bufmgr, name, size, alignment);
+}
+
+inline static brw_bo *brw_bo_create_tiled(brw_batch *batch,
+ const char *name,
+ uint32_t width,
+ uint32_t height,
+ uint32_t cpp,
+ uint32_t *tiling,
+ uint32_t *pitch,
+ unsigned flags)
+{
+ unsigned long __pitch;
+ brw_bo *bo = drm_intel_bo_alloc_tiled(batch->bufmgr, name,
+ width, height, cpp,
+ tiling, &__pitch,
+ flags);
+ *pitch = __pitch;
+ return bo;
+}
+
+inline static brw_bo *brw_bo_create_from_name(brw_batch *batch,
+ const char *name,
+ uint32_t global_name)
+{
+ return drm_intel_bo_gem_create_from_name(batch->bufmgr, name, global_name);
+}
+
inline static brw_bo *brw_bo_get(brw_bo *bo)
{
drm_intel_bo_reference(bo);
diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c
index 942f3f99eb..02d053e072 100644
--- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
+++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
@@ -385,8 +385,7 @@ gen7_enable_hw_binding_tables(struct brw_context *brw)
* "A maximum of 16,383 Binding tables are allowed in any batch buffer"
*/
static const int max_size = 16383 * 4;
- brw->hw_bt_pool.bo = drm_intel_bo_alloc(brw->batch.bufmgr, "hw_bt",
- max_size, 64);
+ brw->hw_bt_pool.bo = brw_bo_create(&brw->batch, "hw_bt", max_size, 64, 0);
brw->hw_bt_pool.next_offset = 0;
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 641a2f533e..a4b9880316 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1609,8 +1609,7 @@ intel_process_dri2_buffer(struct brw_context *brw,
buffer->cpp, buffer->pitch);
}
- bo = drm_intel_bo_gem_create_from_name(brw->batch.bufmgr, buffer_name,
- buffer->name);
+ bo = brw_bo_create_from_name(&brw->batch, buffer_name, buffer->name);
if (!bo) {
fprintf(stderr,
"Failed to open BO for returned DRI2 buffer "
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index d0f66daaa1..5aa0c8d2ec 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -339,7 +339,7 @@ brw_get_scratch_bo(struct brw_context *brw,
}
if (!old_bo) {
- *scratch_bo = drm_intel_bo_alloc(brw->batch.bufmgr, "scratch bo", size, 4096);
+ *scratch_bo = brw_bo_create(&brw->batch, "scratch bo", size, 4096, 0);
}
}
@@ -359,8 +359,9 @@ brw_alloc_stage_scratch(struct brw_context *brw,
brw_bo_put(stage_state->scratch_bo);
stage_state->scratch_bo =
- drm_intel_bo_alloc(brw->batch.bufmgr, "shader scratch space",
- per_thread_size * thread_count, 4096);
+ brw_bo_create(&brw->batch, "shader scratch space",
+ per_thread_size * thread_count, 4096,
+ BO_ALLOC_FOR_RENDER);
}
}
@@ -388,9 +389,9 @@ void
brw_init_shader_time(struct brw_context *brw)
{
const int max_entries = 2048;
- brw->shader_time.bo =
- drm_intel_bo_alloc(brw->batch.bufmgr, "shader time",
- max_entries * SHADER_TIME_STRIDE * 3, 4096);
+ brw->shader_time.bo = brw_bo_create(&brw->batch, "shader time",
+ max_entries * SHADER_TIME_STRIDE * 3,
+ 4096, 0);
brw->shader_time.names = rzalloc_array(brw, const char *, max_entries);
brw->shader_time.ids = rzalloc_array(brw, int, max_entries);
brw->shader_time.types = rzalloc_array(brw, enum shader_time_shader_type,
diff --git a/src/mesa/drivers/dri/i965/brw_program_cache.c b/src/mesa/drivers/dri/i965/brw_program_cache.c
index d1a10a78c6..d0e1357a84 100644
--- a/src/mesa/drivers/dri/i965/brw_program_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_program_cache.c
@@ -172,7 +172,7 @@ brw_cache_new_bo(struct brw_cache *cache, uint32_t new_size)
struct brw_context *brw = cache->brw;
brw_bo *new_bo;
- new_bo = drm_intel_bo_alloc(brw->batch.bufmgr, "program cache", new_size, 64);
+ new_bo = brw_bo_create(&brw->batch, "program cache", new_size, 64, 0);
if (brw->has_llc)
drm_intel_gem_bo_map_unsynchronized(new_bo);
@@ -346,7 +346,7 @@ brw_init_caches(struct brw_context *brw)
cache->items =
calloc(cache->size, sizeof(struct brw_cache_item *));
- cache->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "program cache", 4096, 64);
+ cache->bo = brw_bo_create(&brw->batch, "program cache", 4096, 64, 0);
if (brw->has_llc)
drm_intel_gem_bo_map_unsynchronized(cache->bo);
}
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 52a99ab918..1bf3416fe5 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -233,7 +233,7 @@ brw_begin_query(struct gl_context *ctx, struct gl_query_object *q)
* the system was doing other work, such as running other applications.
*/
brw_bo_put(query->bo);
- query->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "timer query", 4096, 4096);
+ query->bo = brw_bo_create(&brw->batch, "timer query", 4096, 4096, 0);
brw_write_timestamp(brw, query->bo, 0);
break;
@@ -391,7 +391,7 @@ ensure_bo_has_space(struct gl_context *ctx, struct brw_query_object *query)
brw_queryobj_get_results(ctx, query);
}
- query->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "query", 4096, 1);
+ query->bo = brw_bo_create(&brw->batch, "query", 4096, 0, 0);
query->last_index = 0;
}
}
@@ -477,7 +477,7 @@ brw_query_counter(struct gl_context *ctx, struct gl_query_object *q)
assert(q->Target == GL_TIMESTAMP);
brw_bo_put(query->bo);
- query->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "timestamp query", 4096, 4096);
+ query->bo = brw_bo_create(&brw->batch, "timestamp query", 4096, 4096, 0);
brw_write_timestamp(brw, query->bo, 0);
query->flushed = false;
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index 4191ae51b0..82b8baee79 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -277,7 +277,7 @@ gen6_begin_query(struct gl_context *ctx, struct gl_query_object *q)
/* Since we're starting a new query, we need to throw away old results. */
brw_bo_put(query->bo);
- query->bo = drm_intel_bo_alloc(brw->batch.bufmgr, "query results", 4096, 4096);
+ query->bo = brw_bo_create(&brw->batch, "query results", 4096, 4096, 0);
/* For ARB_query_buffer_object: The result is not available */
set_query_availability(brw, query, false);
diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c b/src/mesa/drivers/dri/i965/gen6_sol.c
index 69153aed5f..7aac697915 100644
--- a/src/mesa/drivers/dri/i965/gen6_sol.c
+++ b/src/mesa/drivers/dri/i965/gen6_sol.c
@@ -195,9 +195,9 @@ brw_new_transform_feedback(struct gl_context *ctx, GLuint name)
_mesa_init_transform_feedback_object(&brw_obj->base, name);
brw_obj->offset_bo =
- drm_intel_bo_alloc(brw->batch.bufmgr, "transform feedback offsets", 16, 64);
+ brw_bo_create(&brw->batch, "transform feedback offsets", 4096, 64, 0);
brw_obj->prim_count_bo =
- drm_intel_bo_alloc(brw->batch.bufmgr, "xfb primitive counts", 4096, 64);
+ brw_bo_create(&brw->batch, "xfb primitive counts", 4096, 64, 0);
return &brw_obj->base;
}
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 230d1763dc..01b0d4fe2c 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -80,7 +80,7 @@ intel_batchbuffer_reset(struct brw_batch *batch, bool has_llc)
brw_batch_clear_dirty(batch);
- batch->bo = drm_intel_bo_alloc(batch->bufmgr, "batchbuffer", BATCH_SZ, 4096);
+ batch->bo = brw_bo_create(batch, "batchbuffer", BATCH_SZ, 4096, 0);
if (has_llc) {
drm_intel_bo_map(batch->bo, true);
batch->map = batch->bo->virtual;
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index b077a3d828..86c579d081 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -98,8 +98,8 @@ static void
alloc_buffer_object(struct brw_context *brw,
struct intel_buffer_object *intel_obj)
{
- intel_obj->buffer = drm_intel_bo_alloc(brw->batch.bufmgr, "bufferobj",
- intel_obj->Base.Size, 64);
+ intel_obj->buffer =
+ brw_bo_create(&brw->batch, "bufferobj", intel_obj->Base.Size, 64, 0);
/* the buffer might be bound as a uniform buffer, need to update it
*/
@@ -285,7 +285,7 @@ brw_buffer_subdata(struct gl_context *ctx,
intel_obj->gpu_active_start,
intel_obj->gpu_active_end);
brw_bo *temp_bo =
- drm_intel_bo_alloc(brw->batch.bufmgr, "subdata temp", size, 64);
+ brw_bo_create(&brw->batch, "subdata temp", size, 64, 0);
drm_intel_bo_subdata(temp_bo, 0, size, data);
@@ -422,11 +422,11 @@ brw_map_buffer_range(struct gl_context *ctx,
const unsigned alignment = ctx->Const.MinMapBufferAlignment;
intel_obj->map_extra[index] = (uintptr_t) offset % alignment;
- intel_obj->range_map_bo[index] = drm_intel_bo_alloc(brw->batch.bufmgr,
- "BO blit temp",
- length +
- intel_obj->map_extra[index],
- alignment);
+ intel_obj->range_map_bo[index] = brw_bo_create(&brw->batch,
+ "BO blit temp",
+ length +
+ intel_obj->map_extra[index],
+ alignment, 0);
if (brw->has_llc) {
brw_bo_map(brw, intel_obj->range_map_bo[index],
(access & GL_MAP_WRITE_BIT) != 0, "range-map");
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index abd9517260..e8f94aa65d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -574,9 +574,9 @@ intel_lower_compressed_format(struct brw_context *brw, mesa_format format)
}
/* This function computes Yf/Ys tiled bo size, alignment and pitch. */
-static unsigned long
-intel_get_yf_ys_bo_size(struct intel_mipmap_tree *mt, unsigned *alignment,
- unsigned long *pitch)
+static uint64_t
+intel_get_yf_ys_bo_size(struct intel_mipmap_tree *mt,
+ uint32_t *alignment, uint32_t *pitch)
{
uint32_t tile_width, tile_height;
unsigned long stride, size, aligned_y;
@@ -641,29 +641,28 @@ miptree_create(struct brw_context *brw,
if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD)
alloc_flags |= BO_ALLOC_FOR_RENDER;
- unsigned long pitch;
+ uint32_t pitch;
mt->etc_format = etc_format;
if (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) {
- unsigned alignment = 0;
- unsigned long size;
+ uint32_t alignment;
+ uint64_t size;
size = intel_get_yf_ys_bo_size(mt, &alignment, &pitch);
assert(size);
- mt->bo = drm_intel_bo_alloc_for_render(brw->batch.bufmgr, "miptree",
- size, alignment);
+ mt->bo = brw_bo_create(&brw->batch, "miptree", size, alignment, 0);
} else {
if (format == MESA_FORMAT_S_UINT8) {
/* Align to size of W tile, 64x64. */
- mt->bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "miptree",
- ALIGN(mt->total_width, 64),
- ALIGN(mt->total_height, 64),
- mt->cpp, &mt->tiling, &pitch,
- alloc_flags);
+ mt->bo = brw_bo_create_tiled(&brw->batch, "miptree",
+ ALIGN(mt->total_width, 64),
+ ALIGN(mt->total_height, 64),
+ mt->cpp, &mt->tiling, &pitch,
+ alloc_flags);
} else {
- mt->bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "miptree",
- mt->total_width, mt->total_height,
- mt->cpp, &mt->tiling, &pitch,
- alloc_flags);
+ mt->bo = brw_bo_create_tiled(&brw->batch, "miptree",
+ mt->total_width, mt->total_height,
+ mt->cpp, &mt->tiling, &pitch,
+ alloc_flags);
}
}
@@ -696,7 +695,6 @@ intel_miptree_create(struct brw_context *brw,
*/
if (brw->gen < 6 && mt->bo->size >= brw->max_gtt_map_object_size &&
mt->tiling == I915_TILING_Y) {
- unsigned long pitch = mt->pitch;
const uint32_t alloc_flags =
(layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD) ?
BO_ALLOC_FOR_RENDER : 0;
@@ -705,10 +703,9 @@ intel_miptree_create(struct brw_context *brw,
mt->tiling = I915_TILING_X;
brw_bo_put(mt->bo);
- mt->bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "miptree",
- mt->total_width, mt->total_height, mt->cpp,
- &mt->tiling, &pitch, alloc_flags);
- mt->pitch = pitch;
+ mt->bo = brw_bo_create_tiled(&brw->batch, "miptree",
+ mt->total_width, mt->total_height, mt->cpp,
+ &mt->tiling, &mt->pitch, alloc_flags);
}
mt->offset = 0;
@@ -1753,12 +1750,12 @@ intel_gen7_hiz_buf_create(struct brw_context *brw,
hz_height = DIV_ROUND_UP(hz_qpitch * Z0, 2 * 8) * 8;
}
- unsigned long pitch;
+ uint32_t pitch;
uint32_t tiling = I915_TILING_Y;
- buf->aux_base.bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "hiz",
- hz_width, hz_height, 1,
- &tiling, &pitch,
- BO_ALLOC_FOR_RENDER);
+ buf->aux_base.bo = brw_bo_create_tiled(&brw->batch, "hiz",
+ hz_width, hz_height, 1,
+ &tiling, &pitch,
+ BO_ALLOC_FOR_RENDER);
if (!buf->aux_base.bo) {
free(buf);
return NULL;
@@ -1850,12 +1847,12 @@ intel_gen8_hiz_buf_create(struct brw_context *brw,
hz_height = DIV_ROUND_UP(buf->aux_base.qpitch, 2 * 8) * 8 * Z0;
}
- unsigned long pitch;
+ uint32_t pitch;
uint32_t tiling = I915_TILING_Y;
- buf->aux_base.bo = drm_intel_bo_alloc_tiled(brw->batch.bufmgr, "hiz",
- hz_width, hz_height, 1,
- &tiling, &pitch,
- BO_ALLOC_FOR_RENDER);
+ buf->aux_base.bo = brw_bo_create_tiled(&brw->batch, "hiz",
+ hz_width, hz_height, 1,
+ &tiling, &pitch,
+ BO_ALLOC_FOR_RENDER);
if (!buf->aux_base.bo) {
free(buf);
return NULL;
diff --git a/src/mesa/drivers/dri/i965/intel_upload.c b/src/mesa/drivers/dri/i965/intel_upload.c
index ce8edcb0b6..4ace69271c 100644
--- a/src/mesa/drivers/dri/i965/intel_upload.c
+++ b/src/mesa/drivers/dri/i965/intel_upload.c
@@ -94,8 +94,8 @@ intel_upload_space(struct brw_context *brw,
}
if (!brw->upload.bo) {
- brw->upload.bo = drm_intel_bo_alloc(brw->batch.bufmgr, "streamed data",
- MAX2(INTEL_UPLOAD_SIZE, size), 4096);
+ brw->upload.bo = brw_bo_create(&brw->batch, "streamed data",
+ MAX2(INTEL_UPLOAD_SIZE, size), 4096, 0);
if (brw->has_llc)
drm_intel_bo_map(brw->upload.bo, true);
else
--
2.11.0
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