[Mesa-dev] [PATCH 50/51] i965: Coalesce relocation read/write domains to a single integer
Chris Wilson
chris at chris-wilson.co.uk
Tue Jan 10 21:24:13 UTC 2017
There are only a handful of distinct cache domains (less than 16), and
internally the kernel simply doesn't differentiate between the GPU cache
domains - for recent kernels we just pass in whether the object is being
written to (for read/write busyness tracking) and whether it requires the
global GTT workaround, essentially 2 bits of information. We can therefore
trim a parameter by coalescing the relocation domains to a single unsigned
bitfield (i.e. 32 bits of read/write domains rather than 64 bits) without
loss of generality.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/intel/blorp/blorp.h | 3 +-
src/mesa/drivers/dri/i965/brw_batch.c | 13 +++----
src/mesa/drivers/dri/i965/brw_batch.h | 19 +++++-----
src/mesa/drivers/dri/i965/brw_binding_tables.c | 8 ++--
src/mesa/drivers/dri/i965/brw_blorp.c | 12 +++---
src/mesa/drivers/dri/i965/brw_cc.c | 2 +-
src/mesa/drivers/dri/i965/brw_clip_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_compute.c | 12 +++---
src/mesa/drivers/dri/i965/brw_conditional_render.c | 6 +--
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_curbe.c | 4 +-
src/mesa/drivers/dri/i965/brw_draw.c | 14 +++----
src/mesa/drivers/dri/i965/brw_draw_upload.c | 16 +++-----
src/mesa/drivers/dri/i965/brw_misc_state.c | 41 +++++++++------------
src/mesa/drivers/dri/i965/brw_pipe_control.c | 8 ++--
src/mesa/drivers/dri/i965/brw_pipelined_register.c | 43 +++++++++-------------
src/mesa/drivers/dri/i965/brw_pipelined_register.h | 4 +-
src/mesa/drivers/dri/i965/brw_sampler_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_sf_state.c | 3 +-
src/mesa/drivers/dri/i965/brw_vs_state.c | 4 +-
src/mesa/drivers/dri/i965/brw_wm_state.c | 4 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 27 ++++++--------
src/mesa/drivers/dri/i965/gen6_constant_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_depth_state.c | 12 ++----
src/mesa/drivers/dri/i965/gen6_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_vs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_wm_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_cs_state.c | 6 +--
src/mesa/drivers/dri/i965/gen7_ds_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_hs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_misc_state.c | 13 ++-----
src/mesa/drivers/dri/i965/gen7_sol_state.c | 7 ++--
src/mesa/drivers/dri/i965/gen7_vs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_depth_state.c | 9 ++---
src/mesa/drivers/dri/i965/gen8_draw_upload.c | 2 +-
src/mesa/drivers/dri/i965/gen8_ds_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_hs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_ps_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_sol_state.c | 4 +-
src/mesa/drivers/dri/i965/gen8_vs_state.c | 2 +-
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 7 ++--
src/mesa/drivers/dri/i965/hsw_queryobj.c | 20 ++++------
src/mesa/drivers/dri/i965/hsw_sol.c | 8 ++--
src/mesa/drivers/dri/i965/intel_blit.c | 28 ++++----------
47 files changed, 164 insertions(+), 229 deletions(-)
diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index 823475b607..bbe1655da5 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -90,8 +90,7 @@ void blorp_batch_finish(struct blorp_batch *batch);
struct blorp_address {
void *buffer;
- uint32_t read_domains;
- uint32_t write_domain;
+ uint32_t domains;
uint32_t offset;
};
diff --git a/src/mesa/drivers/dri/i965/brw_batch.c b/src/mesa/drivers/dri/i965/brw_batch.c
index 515a81bf89..e4d0d4c8b2 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_batch.c
@@ -848,8 +848,7 @@ uint64_t __brw_batch_reloc(struct brw_batch *batch,
uint32_t batch_offset,
struct brw_bo *target_bo,
uint64_t target_offset,
- unsigned read_domains,
- unsigned write_domain)
+ unsigned domains)
{
assert(batch->inside_begin_count);
assert(target_bo->refcnt);
@@ -953,8 +952,8 @@ uint64_t __brw_batch_reloc(struct brw_batch *batch,
batch->reloc[n].delta = target_offset;
batch->reloc[n].target_handle = target_bo->target_handle;
batch->reloc[n].presumed_offset = target_bo->offset;
- batch->reloc[n].read_domains = read_domains;
- batch->reloc[n].write_domain = write_domain;
+ batch->reloc[n].read_domains = domains & 0xffff;
+ batch->reloc[n].write_domain = domains >> 16;
/* If we haven't added the batch to the execobject array yet, we
* will have to process all the relocations pointing to the
@@ -973,7 +972,7 @@ uint64_t __brw_batch_reloc(struct brw_batch *batch,
* can optimised reading the buffer on the CPU whilst it is only being
* read by the GPU.
*/
- if (write_domain && !target_bo->dirty) {
+ if (domains >> 16 && !target_bo->dirty) {
__DBG(("%d:%s: dirty handle=%d\n", gettid(), __func__,
target_bo->handle));
assert(target_bo != batch->bo);
@@ -986,7 +985,7 @@ uint64_t __brw_batch_reloc(struct brw_batch *batch,
target_bo->dirty = true;
if (has_lut(batch)) {
target_bo->exec->flags |= EXEC_OBJECT_WRITE;
- if (write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
+ if ((domains >> 16) == I915_GEM_DOMAIN_INSTRUCTION &&
batch->needs_pipecontrol_ggtt_wa)
target_bo->exec->flags |= EXEC_OBJECT_NEEDS_GTT;
}
@@ -1041,7 +1040,7 @@ static uint32_t __brw_batch_emit_seqno(struct brw_batch *batch,
__brw_batch_reloc(batch,
(char *)out - (char *)batch->map,
batch->seqno_bo, offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
+ BRW_DOMAINS(INSTRUCTION, false));
if (batch->needs_pipecontrol_ggtt_wa)
batch->seqno_bo->exec->flags |= EXEC_OBJECT_NEEDS_GTT;
if (gen >= 8) {
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h b/src/mesa/drivers/dri/i965/brw_batch.h
index 074a13f550..c8fa0fa531 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -213,25 +213,26 @@ brw_reloc_address(brw_bo *bo, uint64_t offset)
/** Add a relocation entry to the current batch
* XXX worth specialising 32bit variant?
*/
+#define __BRW_DOMAINS(read, write) (((write) << 16) | (read))
+#define BRW_DOMAINS(read, write) \
+ __BRW_DOMAINS(I915_GEM_DOMAIN_##read, write ? I915_GEM_DOMAIN_##read : 0)
uint64_t __brw_batch_reloc(struct brw_batch *batch,
uint32_t batch_offset,
struct brw_bo *target_bo,
uint64_t target_offset,
- unsigned read_domains,
- unsigned write_domain);
+ unsigned domains);
static inline uint64_t brw_batch_reloc(struct brw_batch *batch,
uint32_t batch_offset,
struct brw_bo *target_bo,
uint64_t target_offset,
- unsigned read_domains,
- unsigned write_domain)
+ unsigned domains)
{
if (target_bo == NULL)
return target_offset;
return __brw_batch_reloc(batch, batch_offset,
target_bo, target_offset,
- read_domains, write_domain);
+ domains);
}
int brw_batch_get_reset_stats(struct brw_batch *batch,
@@ -476,14 +477,14 @@ static inline uint32_t float_as_int(float f)
uint32_t *__map = __brw_batch_check(&brw->batch, n, BLT_RING)
#define OUT_BATCH(dw) *__map++ = (dw)
#define OUT_BATCH_F(f) *__map++ = float_as_int(f)
-#define OUT_RELOC(bo, read, write, delta) \
+#define OUT_RELOC(bo, domains, delta) \
*__map = brw_batch_reloc(&brw->batch, \
4*(__map - brw->batch.map), \
- bo, delta, read, write), __map++
-#define OUT_RELOC64(bo, read, write, delta) \
+ bo, delta, domains), __map++
+#define OUT_RELOC64(bo, domains, delta) \
*(uint64_t *)__map = brw_batch_reloc(&brw->batch, \
4*(__map - brw->batch.map), \
- bo, delta, read, write), __map += 2
+ bo, delta, domains), __map += 2
#define ADVANCE_BATCH() assert(__map == brw->batch.tail); } while(0)
#ifdef __cplusplus
diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c
index 5a21b695c2..df9f97aa21 100644
--- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
+++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
@@ -410,12 +410,12 @@ gen7_enable_hw_binding_tables(struct brw_context *brw)
BEGIN_BATCH(pkt_len);
OUT_BATCH(_3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 | (pkt_len - 2));
if (brw->gen >= 8) {
- OUT_RELOC64(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0, dw1);
+ OUT_RELOC64(brw->hw_bt_pool.bo, BRW_DOMAINS(SAMPLER, false), dw1);
OUT_BATCH(brw->hw_bt_pool.bo->size);
} else {
- OUT_RELOC(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0, dw1);
- OUT_RELOC(brw->hw_bt_pool.bo, I915_GEM_DOMAIN_SAMPLER, 0,
- brw->hw_bt_pool.bo->size);
+ OUT_RELOC(brw->hw_bt_pool.bo, BRW_DOMAINS(SAMPLER, false), dw1);
+ OUT_RELOC(brw->hw_bt_pool.bo, BRW_DOMAINS(SAMPLER, false),
+ brw->hw_bt_pool.bo->size);
}
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 8d58616f59..957bc5b7ce 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -165,9 +165,9 @@ blorp_surf_for_miptree(struct brw_context *brw,
surf->addr = (struct blorp_address) {
.buffer = mt->bo,
.offset = mt->offset,
- .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
- I915_GEM_DOMAIN_SAMPLER,
- .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
+ .domains = (is_render_target ?
+ BRW_DOMAINS(RENDER, true) :
+ BRW_DOMAINS(SAMPLER, false)),
};
if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
@@ -234,9 +234,9 @@ blorp_surf_for_miptree(struct brw_context *brw,
surf->aux_surf = aux_surf;
surf->aux_addr = (struct blorp_address) {
- .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
- I915_GEM_DOMAIN_SAMPLER,
- .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
+ .domains = (is_render_target ?
+ BRW_DOMAINS(RENDER, true) :
+ BRW_DOMAINS(SAMPLER, false)),
};
if (mt->mcs_buf) {
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index af095c5713..19aded0ce9 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -235,7 +235,7 @@ static void upload_cc_unit(struct brw_context *brw)
brw->cc.state_offset +
offsetof(struct brw_cc_unit_state, cc4),
brw->batch.bo, brw->cc.vp_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
+ BRW_DOMAINS(INSTRUCTION, false));
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
}
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index d933b0aebb..cba1093f98 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -138,7 +138,7 @@ brw_upload_clip_unit(struct brw_context *brw)
brw->clip.state_offset +
offsetof(struct brw_clip_unit_state, clip6),
brw->batch.bo, brw->clip.vp_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
+ BRW_DOMAINS(INSTRUCTION, false));
}
/* _NEW_TRANSFORM */
diff --git a/src/mesa/drivers/dri/i965/brw_compute.c b/src/mesa/drivers/dri/i965/brw_compute.c
index da10c6fba6..0c5f76ab00 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -41,13 +41,13 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
brw_bo *bo = brw->compute.num_work_groups_bo;
brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
indirect_offset + 0);
brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
indirect_offset + 4);
brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
indirect_offset + 8);
if (brw->gen > 7)
@@ -66,7 +66,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
/* Load compute_dispatch_indirect_x_size into SRC0 */
brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
+ BRW_DOMAINS(INSTRUCTION, false),
indirect_offset + 0);
/* predicate = (compute_dispatch_indirect_x_size == 0); */
@@ -79,7 +79,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
/* Load compute_dispatch_indirect_y_size into SRC0 */
brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
+ BRW_DOMAINS(INSTRUCTION, false),
indirect_offset + 4);
/* predicate |= (compute_dispatch_indirect_y_size == 0); */
@@ -92,7 +92,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
/* Load compute_dispatch_indirect_z_size into SRC0 */
brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
+ BRW_DOMAINS(INSTRUCTION, false),
indirect_offset + 8);
/* predicate |= (compute_dispatch_indirect_z_size == 0); */
diff --git a/src/mesa/drivers/dri/i965/brw_conditional_render.c b/src/mesa/drivers/dri/i965/brw_conditional_render.c
index 2c73697d5b..63fd8776ac 100644
--- a/src/mesa/drivers/dri/i965/brw_conditional_render.c
+++ b/src/mesa/drivers/dri/i965/brw_conditional_render.c
@@ -68,14 +68,12 @@ set_predicate_for_result(struct brw_context *brw,
brw_load_register_mem64(brw,
MI_PREDICATE_SRC0,
query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- 0, /* write domain */
+ BRW_DOMAINS(INSTRUCTION, false),
8*query->index /* offset */);
brw_load_register_mem64(brw,
MI_PREDICATE_SRC1,
query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- 0, /* write domain */
+ BRW_DOMAINS(INSTRUCTION, false),
8*(query->index+1) /* offset */);
if (inverted)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index cd31b730f5..ee934f6bd2 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1577,7 +1577,7 @@ brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
return brw_batch_reloc(&brw->batch, state_offset,
brw->cache.bo, prog_offset,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
+ BRW_DOMAINS(INSTRUCTION, false));
}
bool brw_do_cubemap_normalize(struct exec_list *instructions);
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index fc10062c98..72a1ac8217 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -301,8 +301,8 @@ emit:
} else {
OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2));
OUT_RELOC(brw->curbe.curbe_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- (brw->curbe.total_size - 1) + brw->curbe.curbe_offset);
+ BRW_DOMAINS(INSTRUCTION, false),
+ (brw->curbe.total_size - 1) + brw->curbe.curbe_offset);
}
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index e2007774d7..5ebecff87e 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -205,7 +205,7 @@ brw_emit_prim(struct brw_context *brw,
brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT,
xfb_obj->prim_count_bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
stream * sizeof(uint32_t));
BEGIN_BATCH(9);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (9 - 2));
@@ -227,25 +227,25 @@ brw_emit_prim(struct brw_context *brw,
indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
prim->indirect_offset + 0);
brw_load_register_mem(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
prim->indirect_offset + 4);
brw_load_register_mem(brw, GEN7_3DPRIM_START_VERTEX, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
prim->indirect_offset + 8);
if (prim->indexed) {
brw_load_register_mem(brw, GEN7_3DPRIM_BASE_VERTEX, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
prim->indirect_offset + 12);
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
prim->indirect_offset + 16);
} else {
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
+ BRW_DOMAINS(VERTEX, false),
prim->indirect_offset + 12);
brw_load_register_imm32(brw, GEN7_3DPRIM_BASE_VERTEX, 0);
}
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 8f94f6f265..7b84b3be3a 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -750,7 +750,7 @@ brw_emit_vertex_buffer_state(struct brw_context *brw,
stride);
OUT_BATCH(dw0 | (stride << BRW_VB0_PITCH_SHIFT));
if (brw->gen >= 8) {
- OUT_RELOC64(bo, I915_GEM_DOMAIN_VERTEX, 0, start_offset);
+ OUT_RELOC64(bo, BRW_DOMAINS(VERTEX, false), start_offset);
/* From the BSpec: 3D Pipeline Stages - 3D Pipeline Geometry -
* Vertex Fetch (VF) Stage - State
*
@@ -761,7 +761,7 @@ brw_emit_vertex_buffer_state(struct brw_context *brw,
*/
OUT_BATCH(end_offset - start_offset);
} else if (brw->gen >= 5) {
- OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, start_offset);
+ OUT_RELOC(bo, BRW_DOMAINS(VERTEX, false), start_offset);
/* From the BSpec: 3D Pipeline Stages - 3D Pipeline Geometry -
* Vertex Fetch (VF) Stage - State
*
@@ -770,10 +770,10 @@ brw_emit_vertex_buffer_state(struct brw_context *brw,
* last valid byte of the buffer is determined by
* "VBState.EndAddress + 1".
*/
- OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, end_offset - 1);
+ OUT_RELOC(bo, BRW_DOMAINS(VERTEX, false), end_offset - 1);
OUT_BATCH(step_rate);
} else {
- OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, start_offset);
+ OUT_RELOC(bo, BRW_DOMAINS(VERTEX, false), start_offset);
OUT_BATCH(0);
OUT_BATCH(step_rate);
}
@@ -1152,12 +1152,8 @@ brw_emit_index_buffer(struct brw_context *brw)
cut_index_setting |
brw_get_index_type(index_buffer->type) |
1);
- OUT_RELOC(brw->ib.bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- 0);
- OUT_RELOC(brw->ib.bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- brw->ib.size - 1);
+ OUT_RELOC(brw->ib.bo, BRW_DOMAINS(VERTEX, false), 0);
+ OUT_RELOC(brw->ib.bo, BRW_DOMAINS(VERTEX, false), brw->ib.size - 1);
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 9197057e49..4e4dc8a1bf 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -86,20 +86,20 @@ upload_pipelined_state_pointers(struct brw_context *brw)
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false),
brw->vs.base.state_offset);
if (brw->ff_gs.prog_active)
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false),
brw->ff_gs.state_offset | 1);
else
OUT_BATCH(0);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false),
brw->clip.state_offset | 1);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false),
brw->sf.state_offset);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false),
brw->wm.base.state_offset);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false),
brw->cc.state_offset);
ADVANCE_BATCH();
@@ -612,7 +612,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
if (depth_mt) {
OUT_RELOC(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
depth_offset);
} else {
OUT_BATCH(0);
@@ -649,7 +649,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(hiz_mt->pitch - 1);
OUT_RELOC(hiz_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
brw->depthstencil.hiz_offset);
ADVANCE_BATCH();
} else {
@@ -671,7 +671,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
*/
OUT_BATCH(2 * stencil_mt->pitch - 1);
OUT_RELOC(stencil_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
brw->depthstencil.stencil_offset);
ADVANCE_BATCH();
} else {
@@ -1057,18 +1057,14 @@ brw_upload_state_base_address(struct brw_context *brw)
OUT_BATCH(0);
OUT_BATCH(mocs_wb << 16);
/* Surface state base address: */
- OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
- mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->batch.bo, BRW_DOMAINS(SAMPLER, false), mocs_wb << 4 | 1);
/* Dynamic state base address: */
- OUT_RELOC64(brw->batch.bo,
- I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
- mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->batch.bo, BRW_DOMAINS(RENDER, false), mocs_wb << 4 | 1);
/* Indirect object base address: MEDIA_OBJECT data */
OUT_BATCH(mocs_wb << 4 | 1);
OUT_BATCH(0);
/* Instruction base address: shader kernels (incl. SIP) */
- OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->cache.bo, BRW_DOMAINS(INSTRUCTION, 0), mocs_wb << 4 | 1);
/* General state buffer size */
OUT_BATCH(0xfffff001);
@@ -1096,7 +1092,7 @@ brw_upload_state_base_address(struct brw_context *brw)
* BINDING_TABLE_STATE
* SURFACE_STATE
*/
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(SAMPLER, false), 1);
/* Dynamic state base address:
* SAMPLER_STATE
* SAMPLER_BORDER_COLOR_STATE
@@ -1107,11 +1103,10 @@ brw_upload_state_base_address(struct brw_context *brw)
* Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
* Disable is clear, which we rely on)
*/
- OUT_RELOC(brw->batch.bo, (I915_GEM_DOMAIN_RENDER |
- I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(INSTRUCTION, false), 1);
OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
- OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->cache.bo, BRW_DOMAINS(INSTRUCTION, false),
1); /* Instruction base address: shader kernels (incl. SIP) */
OUT_BATCH(1); /* General state upper bound */
@@ -1128,10 +1123,10 @@ brw_upload_state_base_address(struct brw_context *brw)
BEGIN_BATCH(8);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
OUT_BATCH(1); /* General state base address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(SAMPLER, false),
1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
- OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->cache.bo, BRW_DOMAINS(INSTRUCTION, false),
1); /* Instruction base address */
OUT_BATCH(0xfffff001); /* General state upper bound */
OUT_BATCH(1); /* Indirect object upper bound */
@@ -1141,7 +1136,7 @@ brw_upload_state_base_address(struct brw_context *brw)
BEGIN_BATCH(6);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
OUT_BATCH(1); /* General state base address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
+ OUT_RELOC(brw->batch.bo, BRW_DOMAINS(SAMPLER, false),
1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
OUT_BATCH(1); /* General state upper bound */
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 40102f9aa6..c33e9ea31e 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -212,8 +212,7 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
OUT_BATCH(flags);
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC64(bo, BRW_DOMAINS(INSTRUCTION, true), offset);
OUT_BATCH(lower_32_bits(imm));
OUT_BATCH(upper_32_bits(imm));
ADVANCE_BATCH();
@@ -228,15 +227,14 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
OUT_BATCH(flags);
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- gen6_gtt | offset);
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true), gen6_gtt | offset);
OUT_BATCH(lower_32_bits(imm));
OUT_BATCH(upper_32_bits(imm));
ADVANCE_BATCH();
} else {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true),
PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
OUT_BATCH(lower_32_bits(imm));
OUT_BATCH(upper_32_bits(imm));
diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.c b/src/mesa/drivers/dri/i965/brw_pipelined_register.c
index 86ec3cd3bd..128f2e0eb3 100644
--- a/src/mesa/drivers/dri/i965/brw_pipelined_register.c
+++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.c
@@ -29,7 +29,7 @@ static void
load_sized_register_mem(struct brw_context *brw,
uint32_t reg,
brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
+ unsigned domains,
uint32_t offset,
int size)
{
@@ -43,7 +43,7 @@ load_sized_register_mem(struct brw_context *brw,
for (i = 0; i < size; i++) {
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg + i * 4);
- OUT_RELOC64(bo, read_domains, write_domain, offset + i * 4);
+ OUT_RELOC64(bo, domains, offset + i * 4);
}
ADVANCE_BATCH();
} else {
@@ -51,7 +51,7 @@ load_sized_register_mem(struct brw_context *brw,
for (i = 0; i < size; i++) {
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg + i * 4);
- OUT_RELOC(bo, read_domains, write_domain, offset + i * 4);
+ OUT_RELOC(bo, domains, offset + i * 4);
}
ADVANCE_BATCH();
}
@@ -61,20 +61,20 @@ void
brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
+ unsigned domains,
uint32_t offset)
{
- load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 1);
+ load_sized_register_mem(brw, reg, bo, domains, offset, 1);
}
void
brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
+ unsigned domains,
uint32_t offset)
{
- load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 2);
+ load_sized_register_mem(brw, reg, bo, domains, offset, 2);
}
/*
@@ -90,15 +90,13 @@ brw_store_register_mem32(struct brw_context *brw,
BEGIN_BATCH(4);
OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg);
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC64(bo, BRW_DOMAINS(INSTRUCTION, true), offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg);
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true), offset);
ADVANCE_BATCH();
}
}
@@ -119,23 +117,20 @@ brw_store_register_mem64(struct brw_context *brw,
BEGIN_BATCH(8);
OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg);
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC64(bo, BRW_DOMAINS(INSTRUCTION, true), offset);
OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg + sizeof(uint32_t));
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ OUT_RELOC64(bo, BRW_DOMAINS(INSTRUCTION, true),
offset + sizeof(uint32_t));
ADVANCE_BATCH();
} else {
BEGIN_BATCH(6);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg);
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true), offset);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg + sizeof(uint32_t));
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset + sizeof(uint32_t));
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true), offset + sizeof(uint32_t));
ADVANCE_BATCH();
}
}
@@ -217,12 +212,10 @@ brw_store_data_imm32(struct brw_context *brw, brw_bo *bo,
BEGIN_BATCH(4);
OUT_BATCH(MI_STORE_DATA_IMM | (4 - 2));
if (brw->gen >= 8)
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC64(bo, BRW_DOMAINS(INSTRUCTION, true), offset);
else {
OUT_BATCH(0); /* MBZ */
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true), offset);
}
OUT_BATCH(imm);
ADVANCE_BATCH();
@@ -240,12 +233,10 @@ brw_store_data_imm64(struct brw_context *brw, brw_bo *bo,
BEGIN_BATCH(5);
OUT_BATCH(MI_STORE_DATA_IMM | (5 - 2));
if (brw->gen >= 8)
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC64(bo, BRW_DOMAINS(INSTRUCTION, true), offset);
else {
OUT_BATCH(0); /* MBZ */
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true), offset);
}
OUT_BATCH(imm & 0xffffffffu);
OUT_BATCH(imm >> 32);
diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.h b/src/mesa/drivers/dri/i965/brw_pipelined_register.h
index 208654c2e5..dbccc3fdea 100644
--- a/src/mesa/drivers/dri/i965/brw_pipelined_register.h
+++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.h
@@ -31,12 +31,12 @@ extern "C" {
void brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
+ unsigned domains,
uint32_t offset);
void brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
+ unsigned domains,
uint32_t offset);
void brw_store_register_mem32(struct brw_context *brw,
brw_bo *bo, uint32_t reg, uint32_t offset);
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index e247ff66f1..97ca4c0a39 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -103,7 +103,7 @@ brw_emit_sampler_state(struct brw_context *brw,
if (brw->gen < 6) {
ss[2] = brw_batch_reloc(&brw->batch, batch_offset_for_sampler_state + 8,
brw->batch.bo, border_color_offset,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ BRW_DOMAINS(SAMPLER, false));
} else
ss[2] = border_color_offset;
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index f8c4209d1d..f61a7e0633 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -202,8 +202,7 @@ static void upload_sf_unit( struct brw_context *brw )
offsetof(struct brw_sf_unit_state, sf5),
brw->batch.bo,
brw->sf.vp_offset | sf->dw5,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
-
+ BRW_DOMAINS(INSTRUCTION, false));
/* _NEW_POLYGON */
switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index d4ef06fd1d..fa82d0fa39 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -88,7 +88,7 @@ brw_upload_vs_unit(struct brw_context *brw)
offsetof(struct brw_vs_unit_state, thread2),
stage_state->scratch_bo,
ffs(stage_state->per_thread_scratch) - 11,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
vs->thread3.urb_entry_read_length = vue_prog_data->urb_read_length;
vs->thread3.const_urb_entry_read_length = prog_data->curb_read_length;
@@ -161,7 +161,7 @@ brw_upload_vs_unit(struct brw_context *brw)
offsetof(struct brw_vs_unit_state, vs5),
brw->batch.bo,
stage_state->sampler_offset | sampler_count,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
+ BRW_DOMAINS(INSTRUCTION, false));
}
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 5054674db5..4f813f5ac0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -137,7 +137,7 @@ brw_upload_wm_unit(struct brw_context *brw)
offsetof(struct brw_wm_unit_state, thread2),
brw->wm.base.scratch_bo,
ffs(brw->wm.base.per_thread_scratch) - 11,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
wm->thread3.dispatch_grf_start_reg =
prog_data->base.dispatch_grf_start_reg;
@@ -163,7 +163,7 @@ brw_upload_wm_unit(struct brw_context *brw)
offsetof(struct brw_wm_unit_state, wm4),
brw->batch.bo,
brw->wm.base.sampler_offset | wm->dw4,
- I915_GEM_DOMAIN_INSTRUCTION, 0);
+ BRW_DOMAINS(INSTRUCTION, false));
}
/* BRW_NEW_FRAGMENT_PROGRAM */
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 6a7f88dcee..5844e512d2 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -76,7 +76,7 @@ brw_emit_surface_state(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t flags,
GLenum target, struct isl_view view,
uint32_t mocs, uint32_t *surf_offset, int surf_index,
- unsigned read_domains, unsigned write_domains)
+ unsigned domains)
{
uint32_t tile_x = mt->level[0].slice[0].x_offset;
uint32_t tile_y = mt->level[0].slice[0].y_offset;
@@ -165,7 +165,7 @@ brw_emit_surface_state(struct brw_context *brw,
.address = brw_batch_reloc(&brw->batch,
*surf_offset + brw->isl_dev.ss.addr_offset,
mt->bo, offset,
- read_domains, write_domains),
+ domains),
.aux_surf = aux_surf, .aux_usage = aux_usage,
.aux_address = aux_offset,
.mocs = mocs, .clear_color = clear_color,
@@ -183,7 +183,7 @@ brw_emit_surface_state(struct brw_context *brw,
brw_batch_reloc(&brw->batch,
*surf_offset + brw->isl_dev.ss.aux_addr_offset,
aux_bo, *aux_addr & 0xfff,
- read_domains, write_domains);
+ domains);
}
}
@@ -228,8 +228,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
brw_emit_surface_state(brw, mt, flags, mt->target, view,
rb_mocs[brw->gen],
&offset, surf_index,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
return offset;
}
@@ -637,7 +636,7 @@ brw_update_texture_surface(struct gl_context *ctx,
brw_emit_surface_state(brw, mt, flags, mt->target, view,
tex_mocs[brw->gen],
surf_offset, surf_index,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ BRW_DOMAINS(SAMPLER, false));
}
}
@@ -660,8 +659,7 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
.address = brw_batch_reloc(&brw->batch,
*out_offset + brw->isl_dev.ss.addr_offset,
bo, buffer_offset,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0)),
+ BRW_DOMAINS(SAMPLER, rw)),
.size = buffer_size,
.format = surface_format,
.stride = pitch,
@@ -811,7 +809,7 @@ brw_update_sol_surface(struct brw_context *brw,
BRW_SURFACE_RC_READ_WRITE;
surf[1] = brw_batch_reloc(&brw->batch, *out_offset + 4,
bo, offset_bytes,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
height << BRW_SURFACE_HEIGHT_SHIFT);
surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
@@ -928,7 +926,7 @@ brw_emit_null_surface_state(struct brw_context *brw,
}
surf[1] = brw_batch_reloc(&brw->batch, *out_offset + 4,
bo, 0,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
surf[2] = ((width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
@@ -1000,7 +998,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
mt->bo,
mt->offset +
intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y),
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ BRW_DOMAINS(RENDER, true));
surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
@@ -1190,7 +1188,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
brw_emit_surface_state(brw, irb->mt, flags, target, view,
tex_mocs[brw->gen],
surf_offset, surf_index,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ BRW_DOMAINS(SAMPLER, false));
} else {
brw->vtbl.emit_null_surface_state(
@@ -1736,9 +1734,8 @@ update_image_surface(struct brw_context *brw,
brw_emit_surface_state(brw, mt, flags, mt->target, view,
tex_mocs[brw->gen],
surf_offset, surf_index,
- I915_GEM_DOMAIN_SAMPLER,
- access == GL_READ_ONLY ? 0 :
- I915_GEM_DOMAIN_SAMPLER);
+ BRW_DOMAINS(SAMPLER,
+ access != GL_READ_ONLY));
}
update_texture_image_param(brw, u, surface_idx, param);
diff --git a/src/mesa/drivers/dri/i965/gen6_constant_state.c b/src/mesa/drivers/dri/i965/gen6_constant_state.c
index 3aeafcf3b2..717aa1a64b 100644
--- a/src/mesa/drivers/dri/i965/gen6_constant_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_constant_state.c
@@ -69,7 +69,7 @@ gen7_upload_constant_state(struct brw_context *brw,
/* XXX: When using buffers other than 0, you need to specify the
* graphics virtual address regardless of INSPM/debug bits
*/
- OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_RENDER, 0,
+ OUT_RELOC64(brw->batch.bo, BRW_DOMAINS(RENDER, false),
stage_state->push_const_offset);
OUT_BATCH(0);
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 89ba911e94..bf159a7933 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -122,9 +122,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
/* 3DSTATE_DEPTH_BUFFER dw2 */
if (depth_mt) {
- OUT_RELOC(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC(depth_mt->bo, BRW_DOMAINS(RENDER, true), 0);
} else {
OUT_BATCH(0);
}
@@ -173,9 +171,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(hiz_mt->pitch - 1);
- OUT_RELOC(hiz_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- offset);
+ OUT_RELOC(hiz_mt->bo, BRW_DOMAINS(RENDER, true), offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
@@ -214,9 +210,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
* the stencil buffer is stored with two rows interleaved.
*/
OUT_BATCH(2 * stencil_mt->pitch - 1);
- OUT_RELOC(stencil_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- offset);
+ OUT_RELOC(stencil_mt->bo, BRW_DOMAINS(RENDER, true), offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index df5f9e8c3b..6ea54ff828 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -144,7 +144,7 @@ upload_gs_state(struct brw_context *brw)
if (prog_data->total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0); /* no scratch space */
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 3694b3b141..631b4a1f57 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -129,7 +129,7 @@ upload_vs_state(struct brw_context *brw)
if (prog_data->total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 31f873241c..2257a4ebc8 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -221,7 +221,7 @@ gen6_upload_wm_state(struct brw_context *brw,
OUT_BATCH(dw2);
if (prog_data->base.total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen7_cs_state.c b/src/mesa/drivers/dri/i965/gen7_cs_state.c
index 7572fec30f..2fff78ab90 100644
--- a/src/mesa/drivers/dri/i965/gen7_cs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_cs_state.c
@@ -69,21 +69,21 @@ brw_upload_cs_state(struct brw_context *brw)
* where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
*/
OUT_RELOC64(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else if (brw->is_haswell) {
/* Haswell's Per Thread Scratch Space is in the range [0, 10]
* where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
*/
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 12);
} else {
/* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
* where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
*/
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
stage_state->per_thread_scratch / 1024 - 1);
}
} else {
diff --git a/src/mesa/drivers/dri/i965/gen7_ds_state.c b/src/mesa/drivers/dri/i965/gen7_ds_state.c
index 25e13d265e..73ea55efb1 100644
--- a/src/mesa/drivers/dri/i965/gen7_ds_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_ds_state.c
@@ -84,7 +84,7 @@ gen7_upload_ds_state(struct brw_context *brw)
GEN7_DS_BINDING_TABLE_ENTRY_COUNT));
if (prog_data->total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen7_gs_state.c b/src/mesa/drivers/dri/i965/gen7_gs_state.c
index 12f54b8a78..aac97d0622 100644
--- a/src/mesa/drivers/dri/i965/gen7_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_gs_state.c
@@ -67,7 +67,7 @@ upload_gs_state(struct brw_context *brw)
if (prog_data->total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen7_hs_state.c b/src/mesa/drivers/dri/i965/gen7_hs_state.c
index 851af15e96..5e8e8bada6 100644
--- a/src/mesa/drivers/dri/i965/gen7_hs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_hs_state.c
@@ -86,7 +86,7 @@ gen7_upload_hs_state(struct brw_context *brw)
OUT_BATCH(stage_state->prog_offset);
if (prog_data->total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index c46eb72206..e5440d7a5c 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -113,9 +113,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
/* 3DSTATE_DEPTH_BUFFER dw2 */
if (depth_mt) {
- OUT_RELOC(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC(depth_mt->bo, BRW_DOMAINS(RENDER, true), 0);
} else {
OUT_BATCH(0);
}
@@ -151,10 +149,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH((mocs << 25) |
(hiz_buf->aux_base.pitch - 1));
- OUT_RELOC(hiz_buf->aux_base.bo,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC(hiz_buf->aux_base.bo, BRW_DOMAINS(RENDER, true), 0);
ADVANCE_BATCH();
}
@@ -183,9 +178,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH(enabled |
mocs << 25 |
(2 * stencil_mt->pitch - 1));
- OUT_RELOC(stencil_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC(stencil_mt->bo, BRW_DOMAINS(RENDER, true), 0);
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index 7e00d9fd0f..1af2a5039f 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -81,8 +81,8 @@ upload_3dstate_so_buffers(struct brw_context *brw)
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT) | stride);
- OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
- OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, end);
+ OUT_RELOC(bo, BRW_DOMAINS(RENDER, true), start);
+ OUT_RELOC(bo, BRW_DOMAINS(RENDER, true), end);
ADVANCE_BATCH();
}
}
@@ -603,8 +603,7 @@ gen7_resume_transform_feedback(struct gl_context *ctx,
brw_load_register_mem(brw,
GEN7_SO_WRITE_OFFSET(i),
brw_obj->offset_bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, true),
i * sizeof(uint32_t));
}
}
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index b6c2a9788e..f7762efb16 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -57,7 +57,7 @@ upload_vs_state(struct brw_context *brw)
if (prog_data->total_scratch) {
OUT_RELOC(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index aa964da48e..59fc4a74e1 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -236,7 +236,7 @@ gen7_upload_ps_state(struct brw_context *brw,
OUT_BATCH(dw2);
if (prog_data->base.total_scratch) {
OUT_RELOC(brw->wm.base.scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 30f0f11432..76f67e02ab 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -69,8 +69,7 @@ emit_depth_packets(struct brw_context *brw,
depthbuffer_format << 18 |
(depth_mt ? depth_mt->pitch - 1 : 0));
if (depth_mt) {
- OUT_RELOC64(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ OUT_RELOC64(depth_mt->bo, BRW_DOMAINS(RENDER, true), 0);
} else {
OUT_BATCH(0);
OUT_BATCH(0);
@@ -94,8 +93,7 @@ emit_depth_packets(struct brw_context *brw,
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
OUT_BATCH((depth_mt->hiz_buf->aux_base.pitch - 1) | mocs_wb << 25);
- OUT_RELOC64(depth_mt->hiz_buf->aux_base.bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ OUT_RELOC64(depth_mt->hiz_buf->aux_base.bo, BRW_DOMAINS(RENDER, true), 0);
OUT_BATCH(depth_mt->hiz_buf->aux_base.qpitch >> 2);
ADVANCE_BATCH();
}
@@ -127,8 +125,7 @@ emit_depth_packets(struct brw_context *brw,
*/
OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
(2 * stencil_mt->pitch - 1));
- OUT_RELOC64(stencil_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ OUT_RELOC64(stencil_mt->bo, BRW_DOMAINS(RENDER, true), 0);
OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/gen8_draw_upload.c b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
index 64599103e0..c761bf421f 100644
--- a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
@@ -375,7 +375,7 @@ gen8_emit_index_buffer(struct brw_context *brw)
BEGIN_BATCH(5);
OUT_BATCH(CMD_INDEX_BUFFER << 16 | (5 - 2));
OUT_BATCH(brw_get_index_type(index_buffer->type) | mocs_wb);
- OUT_RELOC64(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
+ OUT_RELOC64(brw->ib.bo, BRW_DOMAINS(VERTEX, false), 0);
OUT_BATCH(brw->ib.size);
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/gen8_ds_state.c b/src/mesa/drivers/dri/i965/gen8_ds_state.c
index 6c3f9469ce..7469f367b9 100644
--- a/src/mesa/drivers/dri/i965/gen8_ds_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ds_state.c
@@ -52,7 +52,7 @@ gen8_upload_ds_state(struct brw_context *brw)
GEN7_DS_BINDING_TABLE_ENTRY_COUNT));
if (prog_data->total_scratch) {
OUT_RELOC64(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c b/src/mesa/drivers/dri/i965/gen8_gs_state.c
index ba32ab82d1..cbb8b4933b 100644
--- a/src/mesa/drivers/dri/i965/gen8_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c
@@ -59,7 +59,7 @@ gen8_upload_gs_state(struct brw_context *brw)
if (prog_data->total_scratch) {
OUT_RELOC64(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen8_hs_state.c b/src/mesa/drivers/dri/i965/gen8_hs_state.c
index dce44e2892..c34e3ae307 100644
--- a/src/mesa/drivers/dri/i965/gen8_hs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_hs_state.c
@@ -53,7 +53,7 @@ gen8_upload_hs_state(struct brw_context *brw)
OUT_BATCH(0);
if (prog_data->total_scratch) {
OUT_RELOC64(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 2d7bfb60be..85836ba01e 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -265,7 +265,7 @@ gen8_upload_ps_state(struct brw_context *brw,
OUT_BATCH(dw3);
if (prog_data->base.total_scratch) {
OUT_RELOC64(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/gen8_sol_state.c b/src/mesa/drivers/dri/i965/gen8_sol_state.c
index 5fbb7c2344..230ffbee6a 100644
--- a/src/mesa/drivers/dri/i965/gen8_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sol_state.c
@@ -78,10 +78,10 @@ gen8_upload_3dstate_so_buffers(struct brw_context *brw)
GEN8_SO_BUFFER_OFFSET_WRITE_ENABLE |
GEN8_SO_BUFFER_OFFSET_ADDRESS_ENABLE |
(mocs_wb << 22));
- OUT_RELOC64(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
+ OUT_RELOC64(bo, BRW_DOMAINS(RENDER, true), start);
OUT_BATCH(xfb_obj->Size[i] / 4 - 1);
OUT_RELOC64(brw_obj->offset_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, true),
i * sizeof(uint32_t));
if (brw_obj->zero_offsets)
OUT_BATCH(0); /* Zero out the offset and write that to offset_bo */
diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c
index ee09dd7577..da3634394d 100644
--- a/src/mesa/drivers/dri/i965/gen8_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c
@@ -58,7 +58,7 @@ upload_vs_state(struct brw_context *brw)
if (prog_data->total_scratch) {
OUT_RELOC64(stage_state->scratch_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
ffs(stage_state->per_thread_scratch) - 11);
} else {
OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 6f40c44e3d..0d34aca45e 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -49,7 +49,7 @@ blorp_emit_reloc(struct blorp_batch *batch,
return __brw_batch_reloc(&brw->batch,
(char *)location - (char *)brw->batch.map,
address.buffer, address.offset + delta,
- address.read_domains, address.write_domain);
+ address.domains);
}
static void
@@ -62,7 +62,7 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
uint64_t reloc_val =
__brw_batch_reloc(&brw->batch, ss_offset,
address.buffer, address.offset + delta,
- address.read_domains, address.write_domain);
+ address.domains);
void *reloc_ptr = (void *)brw->batch.map + ss_offset;
#if GEN_GEN >= 8
@@ -119,8 +119,7 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
*addr = (struct blorp_address) {
.buffer = brw->batch.bo,
- .read_domains = I915_GEM_DOMAIN_VERTEX,
- .write_domain = 0,
+ .domains = BRW_DOMAINS(VERTEX, false),
.offset = offset,
};
diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c b/src/mesa/drivers/dri/i965/hsw_queryobj.c
index 357e57bd9b..d15a554270 100644
--- a/src/mesa/drivers/dri/i965/hsw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/hsw_queryobj.c
@@ -201,8 +201,7 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct brw_query_object *query,
brw_load_register_mem64(brw,
HSW_CS_GPR(0),
query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, false),
(query->index + 2) * sizeof(uint64_t));
return;
}
@@ -220,21 +219,18 @@ hsw_result_to_gpr0(struct gl_context *ctx, struct brw_query_object *query,
brw_load_register_mem64(brw,
HSW_CS_GPR(0),
query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, false),
(query->index + 0) * sizeof(uint64_t));
} else {
brw_load_register_mem64(brw,
HSW_CS_GPR(1),
query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, false),
(query->index + 0) * sizeof(uint64_t));
brw_load_register_mem64(brw,
HSW_CS_GPR(2),
query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, false),
(query->index + 1) * sizeof(uint64_t));
BEGIN_BATCH(5);
@@ -305,7 +301,7 @@ set_predicate(struct brw_context *brw, struct brw_query_object *query)
/* Load query availability into SRC0 */
brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query->bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
+ BRW_DOMAINS(INSTRUCTION, false),
(query->index + 2) * sizeof(uint64_t));
/* predicate = !(query_availability == 0); */
@@ -338,11 +334,9 @@ store_query_result_reg(struct brw_context *brw, brw_bo *bo,
(cmd_size - 2));
OUT_BATCH(reg + 4 * i);
if (brw->gen >= 8) {
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION, offset + 4 * i);
+ OUT_RELOC64(bo, BRW_DOMAINS(INSTRUCTION, true), offset + 4 * i);
} else {
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION, offset + 4 * i);
+ OUT_RELOC(bo, BRW_DOMAINS(INSTRUCTION, true), offset + 4 * i);
}
}
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/hsw_sol.c b/src/mesa/drivers/dri/i965/hsw_sol.c
index aa27585e94..04f5bbf595 100644
--- a/src/mesa/drivers/dri/i965/hsw_sol.c
+++ b/src/mesa/drivers/dri/i965/hsw_sol.c
@@ -92,14 +92,12 @@ tally_prims_written(struct brw_context *brw,
/* GPR0 = Tally */
brw_load_register_imm32(brw, HSW_CS_GPR(0) + 4, 0);
brw_load_register_mem(brw, HSW_CS_GPR(0), obj->prim_count_bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, true),
TALLY_OFFSET + i * sizeof(uint32_t));
if (!obj->base.Paused) {
/* GPR1 = Start Snapshot */
brw_load_register_mem64(brw, HSW_CS_GPR(1), obj->prim_count_bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, true),
START_OFFSET + i * sizeof(uint64_t));
/* GPR2 = Ending Snapshot */
brw_load_register_reg64(brw, GEN7_SO_NUM_PRIMS_WRITTEN(i), HSW_CS_GPR(2));
@@ -247,7 +245,7 @@ hsw_resume_transform_feedback(struct gl_context *ctx,
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
OUT_RELOC(brw_obj->offset_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+ BRW_DOMAINS(INSTRUCTION, true),
i * sizeof(uint32_t));
ADVANCE_BATCH();
}
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 825643cf0c..0e865797c3 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -724,24 +724,16 @@ intelEmitCopyBlit(struct brw_context *brw,
OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
if (brw->gen >= 8) {
- OUT_RELOC64(dst_buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- dst_offset);
+ OUT_RELOC64(dst_buffer, BRW_DOMAINS(RENDER, true), dst_offset);
} else {
- OUT_RELOC(dst_buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- dst_offset);
+ OUT_RELOC(dst_buffer, BRW_DOMAINS(RENDER, true), dst_offset);
}
OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
OUT_BATCH((uint16_t)src_pitch);
if (brw->gen >= 8) {
- OUT_RELOC64(src_buffer,
- I915_GEM_DOMAIN_RENDER, 0,
- src_offset);
+ OUT_RELOC64(src_buffer, BRW_DOMAINS(RENDER, false), src_offset);
} else {
- OUT_RELOC(src_buffer,
- I915_GEM_DOMAIN_RENDER, 0,
- src_offset);
+ OUT_RELOC(src_buffer, BRW_DOMAINS(RENDER, false), src_offset);
}
ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
@@ -810,13 +802,9 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
if (brw->gen >= 8) {
- OUT_RELOC64(dst_buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- dst_offset);
+ OUT_RELOC64(dst_buffer, BRW_DOMAINS(RENDER, true), dst_offset);
} else {
- OUT_RELOC(dst_buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- dst_offset);
+ OUT_RELOC(dst_buffer, BRW_DOMAINS(RENDER, true), dst_offset);
}
OUT_BATCH(0); /* bg */
OUT_BATCH(fg_color); /* fg */
@@ -958,11 +946,11 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
SET_FIELD(x + chunk_x + chunk_w, BLT_X));
if (brw->gen >= 8) {
OUT_RELOC64(mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
offset);
} else {
OUT_RELOC(mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ BRW_DOMAINS(RENDER, true),
offset);
}
OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
--
2.11.0
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