[Mesa-dev] [PATCH] i965: Use align1 mode for TCS barrier messages.
Jordan Justen
jordan.l.justen at intel.com
Sun Jan 15 20:19:36 UTC 2017
Maybe you should drop 'TCS' from the subject? I think TCS is the
reason for the change, but it doesn't only affect TCS barrier
messages, right?
On 2017-01-15 01:45:45, Kenneth Graunke wrote:
> In commit 7428e6f86ab5 we switched the barrier SEND message's
> destination type to UW to avoid problems in SIMD16 compute shaders.
>
> Tessellation control shaders also use barriers, and in vec4 mode, we
> were emitting them in align16 mode. The simulator warns that only UD,
> D, F, and DF are valid destination types - UW is technically illegal.
UW is okay if using align1? This wording just makes it sound like it
is illegal in all cases.
>
> So, switch to align1 mode. Either mode should work fine.
>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
> src/mesa/drivers/dri/i965/brw_eu_emit.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index 8536a130725..d79a8655c94 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -3587,6 +3587,8 @@ brw_barrier(struct brw_codegen *p, struct brw_reg src)
>
> assert(devinfo->gen >= 7);
>
> + brw_push_insn_state(p);
> + brw_set_default_access_mode(p, BRW_ALIGN_1);
> inst = next_insn(p, BRW_OPCODE_SEND);
> brw_set_dest(p, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
> brw_set_src0(p, inst, src);
> @@ -3598,11 +3600,13 @@ brw_barrier(struct brw_codegen *p, struct brw_reg src)
> false /* header_present */,
> false /* end_of_thread */);
>
> +
Bonus line?
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
> brw_inst_set_gateway_notify(devinfo, inst, 1);
> brw_inst_set_gateway_subfuncid(devinfo, inst,
> BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG);
>
> brw_inst_set_mask_control(devinfo, inst, BRW_MASK_DISABLE);
> + brw_pop_insn_state(p);
> }
>
>
> --
> 2.11.0
>
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