[Mesa-dev] [PATCH 26/27] i965/blorp: Use hiz surface instead of creating copy

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_blorp.c         | 25 ++++++++++++-------------
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  6 ++++++
 2 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 8ecbd0e..f511683 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -114,7 +114,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
                        uint32_t safe_aux_usage,
                        unsigned *level,
                        unsigned start_layer, unsigned num_layers,
-                       struct isl_surf tmp_surfs[2])
+                       struct isl_surf tmp_surfs[1])
 {
    if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
        mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
@@ -172,12 +172,12 @@ blorp_surf_for_miptree(struct brw_context *brw,
 
    surf->aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
 
-   struct isl_surf *aux_surf = &tmp_surfs[1];
+   struct isl_surf *aux_surf = NULL;
 
    if (mt->mcs_buf)
-      *aux_surf = mt->mcs_buf->surf;
-   else
-      intel_miptree_get_aux_isl_surf(brw, mt, surf->aux_usage, aux_surf);
+      aux_surf = &mt->mcs_buf->surf;
+   else if (mt->hiz_buf)
+      aux_surf = &mt->hiz_buf->surf;
 
    if (surf->aux_usage != ISL_AUX_USAGE_NONE) {
       if (surf->aux_usage == ISL_AUX_USAGE_HIZ) {
@@ -248,7 +248,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
              * consulted. Otherwise surf->aux_surf is ignored and there is
              * no need to adjust it.  See blorp_emit_depth_stencil_config().
              */
-            aux_surf->row_pitch = mt->hiz_buf->pitch;
          }
       }
    } else {
@@ -389,12 +388,12 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
                          (1 << ISL_AUX_USAGE_CCS_D);
    }
 
-   struct isl_surf tmp_surfs[4];
+   struct isl_surf tmp_surfs[2];
    struct blorp_surf src_surf, dst_surf;
    blorp_surf_for_miptree(brw, &src_surf, src_mt, false, src_usage_flags,
                           &src_level, src_layer, 1, &tmp_surfs[0]);
    blorp_surf_for_miptree(brw, &dst_surf, dst_mt, true, dst_usage_flags,
-                          &dst_level, dst_layer, 1, &tmp_surfs[2]);
+                          &dst_level, dst_layer, 1, &tmp_surfs[1]);
 
    struct isl_swizzle src_isl_swizzle = {
       .r = swizzle_to_scs(GET_SWZ(src_swizzle, 0)),
@@ -434,7 +433,7 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
        dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
        dst_level, dst_layer, dst_x, dst_y);
 
-   struct isl_surf tmp_surfs[4];
+   struct isl_surf tmp_surfs[2];
    struct blorp_surf src_surf, dst_surf;
    blorp_surf_for_miptree(brw, &src_surf, src_mt, false,
                           (1 << ISL_AUX_USAGE_MCS) |
@@ -443,7 +442,7 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
    blorp_surf_for_miptree(brw, &dst_surf, dst_mt, true,
                           (1 << ISL_AUX_USAGE_MCS) |
                           (1 << ISL_AUX_USAGE_CCS_E),
-                          &dst_level, dst_layer, 1, &tmp_surfs[2]);
+                          &dst_level, dst_layer, 1, &tmp_surfs[1]);
 
    struct blorp_batch batch;
    blorp_batch_init(&brw->blorp, &batch, brw, 0);
@@ -849,7 +848,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
    const unsigned num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
 
    /* We can't setup the blorp_surf until we've allocated the MCS above */
-   struct isl_surf isl_tmp[2];
+   struct isl_surf isl_tmp[1];
    struct blorp_surf surf;
    unsigned level = irb->mt_level;
    blorp_surf_for_miptree(brw, &surf, irb->mt, true,
@@ -936,7 +935,7 @@ brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt,
 
    const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
 
-   struct isl_surf isl_tmp[2];
+   struct isl_surf isl_tmp[1];
    struct blorp_surf surf;
    blorp_surf_for_miptree(brw, &surf, mt, true,
                           (1 << ISL_AUX_USAGE_CCS_E) |
@@ -970,7 +969,7 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 {
    assert(intel_miptree_level_has_hiz(mt, level));
 
-   struct isl_surf isl_tmp[2];
+   struct isl_surf isl_tmp[1];
    struct blorp_surf surf;
    blorp_surf_for_miptree(brw, &surf, mt, true, (1 << ISL_AUX_USAGE_HIZ),
                           &level, layer, 1, isl_tmp);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 09afe92..95a674b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1662,6 +1662,12 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
     */
    buf->qpitch = 0;
 
+   /* Blorp depth state setup relies on ISL surface. Fortunately only
+    * ::row_pitch gets consulted while the rest gets ignored.
+    * See blorp_emit_depth_stencil_config().
+    */
+   buf->surf.row_pitch = buf->pitch;
+
    uint32_t tiling = I915_TILING_Y;
    unsigned long pitch;
    buf->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "hiz",
-- 
2.5.5