[Mesa-dev] [PATCH 18/27] i965/gen6: Allocate hiz directly without miptree
Topi Pohjolainen
topi.pohjolainen at gmail.com
Mon Jan 16 09:13:53 UTC 2017
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 13 +-------
src/mesa/drivers/dri/i965/gen6_depth_state.c | 8 -----
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 43 +++++++++------------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 ----
4 files changed, 15 insertions(+), 54 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 655a961..72ead04 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -230,11 +230,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
surf->aux_addr.buffer = mt->hiz_buf->aux_base.bo;
surf->aux_addr.offset = mt->hiz_buf->aux_base.offset;
- struct intel_mipmap_tree *hiz_mt = mt->hiz_buf->mt;
- if (hiz_mt) {
- assert(brw->gen == 6 &&
- hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);
-
+ if (brw->gen == 6) {
/* gen6 requires the HiZ buffer to be manually offset to the
* right location.
*/
@@ -242,13 +238,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
&surf->surf->phys_level0_sa, surf->surf->dim,
surf->surf->levels, surf->surf->format, *level);
- assert(surf->aux_addr.offset ==
- intel_miptree_get_aligned_offset(
- hiz_mt,
- hiz_mt->level[*level].level_x,
- hiz_mt->level[*level].level_y));
- assert(mt->hiz_buf->aux_base.pitch == hiz_mt->pitch);
-
/* In depth state setup only surf->aux_surf.row_pitch gets
* consulted. Otherwise surf->aux_surf is ignored and there is
* no need to adjust it. See blorp_emit_depth_stencil_config().
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 78683b4..355e37b 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -161,9 +161,6 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
/* Emit hiz buffer. */
if (hiz) {
assert(depth_mt);
- struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt;
-
- assert(hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);
struct isl_surf temp_surf;
intel_miptree_get_isl_surf(brw, mt, &temp_surf);
@@ -175,11 +172,6 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
&temp_surf.phys_level0_sa, temp_surf.dim, temp_surf.levels,
temp_surf.format, lod);
- assert(offset == intel_miptree_get_aligned_offset(
- hiz_mt,
- hiz_mt->level[lod].level_x,
- hiz_mt->level[lod].level_y));
-
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(depth_mt->hiz_buf->aux_base.pitch - 1);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 8b40cfa..3914506 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -946,10 +946,7 @@ intel_miptree_hiz_buffer_free(struct intel_miptree_hiz_buffer *hiz_buf)
if (hiz_buf == NULL)
return;
- if (hiz_buf->mt)
- intel_miptree_release(&hiz_buf->mt);
- else
- drm_intel_bo_unreference(hiz_buf->aux_base.bo);
+ drm_intel_bo_unreference(hiz_buf->aux_base.bo);
free(hiz_buf);
}
@@ -1874,30 +1871,9 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
struct intel_miptree_hiz_buffer *buf = calloc(sizeof(*buf), 1);
- uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
-
- if (brw->gen == 6)
- layout_flags |= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD;
-
if (!buf)
return NULL;
- layout_flags |= MIPTREE_LAYOUT_TILING_ANY;
- buf->mt = intel_miptree_create(brw,
- mt->target,
- mt->format,
- mt->first_level,
- mt->last_level,
- mt->logical_width0,
- mt->logical_height0,
- mt->logical_depth0,
- mt->num_samples,
- layout_flags);
- if (!buf->mt) {
- free(buf);
- return NULL;
- }
-
const uint32_t format = translate_tex_format(brw, mt->format, false);
const unsigned cpp = isl_format_get_layout(format)->bpb / 8;
const unsigned halign = 128 / cpp;
@@ -1914,13 +1890,9 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
const unsigned total_w = brw_get_mipmap_total_width(
phys_level0_sa.width, mt->last_level + 1, halign);
- buf->aux_base.bo = buf->mt->bo;
buf->aux_base.pitch = total_w * cpp;
buf->aux_base.size = total_h * buf->aux_base.pitch;
- assert(buf->aux_base.pitch == buf->mt->pitch);
- assert(buf->aux_base.size == buf->mt->total_height * buf->mt->pitch);
-
/* On gen6 hiz is unconditionally laid out packing all slices
* at each level-of-detail (LOD). This means there is no valid qpitch
* setting. In fact, this is ignored when hardware is setup - there is no
@@ -1928,6 +1900,19 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
*/
buf->aux_base.qpitch = 0;
+ uint32_t tiling = I915_TILING_Y;
+ unsigned long pitch;
+ buf->aux_base.bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "hiz",
+ total_w, total_h, cpp, &tiling,
+ &pitch, BO_ALLOC_FOR_RENDER);
+ if (buf->aux_base.bo) {
+ assert(pitch == buf->aux_base.pitch);
+ assert(tiling == I915_TILING_Y);
+ } else {
+ free(buf);
+ return NULL;
+ }
+
return buf;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 152ae10..4c428cb 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -326,11 +326,6 @@ struct intel_miptree_aux_buffer
struct intel_miptree_hiz_buffer
{
struct intel_miptree_aux_buffer aux_base;
-
- /**
- * Hiz miptree. Used only by Gen6.
- */
- struct intel_mipmap_tree *mt;
};
/* Tile resource modes */
--
2.5.5
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