[Mesa-dev] [PATCH v2 04/20] i965/fs: clamp exec_size to 4 when an instruction has an scalar DF source

[Samuel Iglesias Gonsálvez]

Then the SIMD lowering pass will get rid of any compressed instructions with scalar
source (whether force_writemask_all or not) and we avoid hitting the Gen7 region
decompression bug.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Suggested-by: Francisco Jerez <currojerez at riseup.net>
---
 src/mesa/drivers/dri/i965/brw_fs.cpp | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 95714c16f15..a2ba0fde9fd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -4516,6 +4516,11 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
             const unsigned reg_count = DIV_ROUND_UP(inst->size_written, REG_SIZE);
             max_width = MIN2(max_width, inst->exec_size / reg_count);
          }
+
+         if (type_sz(inst->src[i].type) == 8 &&
+             ((inst->size_read(i) != 0 && inst->size_read(i) <= REG_SIZE) ||
+              is_uniform(inst->src[i])))
+            max_width = MIN2(max_width, 4);
       }
    }
 
-- 
2.11.0