[Mesa-dev] [PATCH v2 05/20] i965: Use <0, 2, 1> region for scalar DF sources on IVB/BYT.

[Samuel Iglesias Gonsálvez]

From: Matt Turner <mattst88 at gmail.com>

On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
region, but on IVB and BYT DF regions must be programmed in terms of
floats. A <0,2,1> region accomplishes this.
---
 src/mesa/drivers/dri/i965/brw_eu_emit.c | 26 ++++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 05c097f66ef..3201c885cb9 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -444,9 +444,16 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
             brw_inst_set_src0_width(devinfo, inst, BRW_WIDTH_1);
             brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
 	 } else {
-            brw_inst_set_src0_hstride(devinfo, inst, reg.hstride);
-            brw_inst_set_src0_width(devinfo, inst, reg.width);
-            brw_inst_set_src0_vstride(devinfo, inst, reg.vstride);
+            if (devinfo->gen == 7 && !devinfo->is_haswell &&
+                reg.type == BRW_REGISTER_TYPE_DF && has_scalar_region(reg)) {
+               brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
+               brw_inst_set_src0_width(devinfo, inst, BRW_WIDTH_2);
+               brw_inst_set_src0_hstride(devinfo, inst, BRW_HORIZONTAL_STRIDE_1);
+            } else {
+               brw_inst_set_src0_vstride(devinfo, inst, reg.vstride);
+               brw_inst_set_src0_width(devinfo, inst, reg.width);
+               brw_inst_set_src0_hstride(devinfo, inst, reg.hstride);
+            }
 	 }
       } else {
          brw_inst_set_src0_da16_swiz_x(devinfo, inst,
@@ -526,9 +533,16 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
             brw_inst_set_src1_width(devinfo, inst, BRW_WIDTH_1);
             brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
 	 } else {
-            brw_inst_set_src1_hstride(devinfo, inst, reg.hstride);
-            brw_inst_set_src1_width(devinfo, inst, reg.width);
-            brw_inst_set_src1_vstride(devinfo, inst, reg.vstride);
+            if (devinfo->gen == 7 && !devinfo->is_haswell &&
+                reg.type == BRW_REGISTER_TYPE_DF && has_scalar_region(reg)) {
+               brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0);
+               brw_inst_set_src1_width(devinfo, inst, BRW_WIDTH_2);
+               brw_inst_set_src1_hstride(devinfo, inst, BRW_HORIZONTAL_STRIDE_1);
+            } else {
+               brw_inst_set_src1_vstride(devinfo, inst, reg.vstride);
+               brw_inst_set_src1_width(devinfo, inst, reg.width);
+               brw_inst_set_src1_hstride(devinfo, inst, reg.hstride);
+            }
 	 }
       } else {
          brw_inst_set_src1_da16_swiz_x(devinfo, inst,
-- 
2.11.0