[Mesa-dev] [PATCH v2 13/20] i965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYT

[Samuel Iglesias Gonsálvez]

From: "Juan A. Suarez Romero" <jasuarez at igalia.com>

In the generator we must generate slightly different code for
Ivybridge/Baytrail, because of the way the stride works in
this hardware.
---
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index ded33ba7cee..62ae1a6cebe 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1946,13 +1946,28 @@ generate_code(struct brw_codegen *p,
 
          brw_set_default_access_mode(p, BRW_ALIGN_1);
 
-         dst.hstride = BRW_HORIZONTAL_STRIDE_2;
+         /* When converting from DF->F, we set destination's stride as 2 as an
+          * aligment requirement. But in IVB/BYT, each DF implicitly writes
+          * two floats, being the first one the converted value. So we don't
+          * need to explicitly set stride 2, but 1.
+          */
+         if (devinfo->gen == 7 && !devinfo->is_haswell)
+            dst.hstride = BRW_HORIZONTAL_STRIDE_1;
+         else
+            dst.hstride = BRW_HORIZONTAL_STRIDE_2;
+
          dst.width = BRW_WIDTH_4;
          src[0].vstride = BRW_VERTICAL_STRIDE_4;
          src[0].width = BRW_WIDTH_4;
          brw_MOV(p, dst, src[0]);
 
          struct brw_reg dst_as_src = dst;
+         /* As we have set horizontal stride 1 instead of 2 in IVB/BYT, we
+          * need to fix it here to have the expected value.
+          */
+         if (devinfo->gen == 7 && !devinfo->is_haswell)
+            dst_as_src.hstride = BRW_HORIZONTAL_STRIDE_2;
+
          dst.hstride = BRW_HORIZONTAL_STRIDE_1;
          dst.width = BRW_WIDTH_8;
          brw_MOV(p, dst, dst_as_src);
-- 
2.11.0