[Mesa-dev] [PATCH 4/4] i965/blorp: Make post draw flush more explicit

[Kenneth Graunke]

On Tuesday, January 17, 2017 8:48:24 PM PST Topi Pohjolainen wrote:
> Blits do not need any special treatment as the target buffer
> object is added to render cache just as one does for normal draw.
> Color clears and resolves in turn require explicit "end of pipe
> synchronization". It is not clear what this means exactly but the
> assumption is that render cache flush with command stream stall
> should be sufficient.
> 
> Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c       | 22 ++++++++++++++++++++++
>  src/mesa/drivers/dri/i965/genX_blorp_exec.c |  5 -----
>  2 files changed, 22 insertions(+), 5 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 8d58616..845abe3 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -908,6 +908,17 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
>        blorp_batch_finish(&batch);
>     }
>  
> +   /*
> +    * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":

   /* Ivybridge PRM Vol 2 ...
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