[Mesa-dev] [PATCH 6/7] radeonsi: always set the TCL1_ACTION_ENA when invalidating L2

[Nicolai Hähnle]

On 20.01.2017 20:07, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> Some CIK-VI docs say this is the default behavior on SI. That doesn't
> answer whether it's also the default behavior on CIK-VI.

Have you actually seen this fix anything? Seems reasonable to me anyway, 
so patches 1-6:

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

>
> Cc: 17.0 13.0 <mesa-stable at lists.freedesktop.org>
> ---
>  src/gallium/drivers/radeonsi/si_state_draw.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
> index 837c025..d296874 100644
> --- a/src/gallium/drivers/radeonsi/si_state_draw.c
> +++ b/src/gallium/drivers/radeonsi/si_state_draw.c
> @@ -843,25 +843,26 @@ void si_emit_cache_flush(struct si_context *sctx)
>  	 * in PFP.
>  	 *
>  	 * cp_coher_cntl should contain all necessary flags except TC flags
>  	 * at this point.
>  	 *
>  	 * SI-CIK don't support L2 write-back.
>  	 */
>  	if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
>  	    (rctx->chip_class <= CIK &&
>  	     (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
> -		/* Invalidate L1 & L2. (L1 is always invalidated)
> +		/* Invalidate L1 & L2. (L1 is always invalidated on SI)
>  		 * WB must be set on VI+ when TC_ACTION is set.
>  		 */
>  		si_emit_surface_sync(rctx, cp_coher_cntl |
>  				     S_0085F0_TC_ACTION_ENA(1) |
> +				     S_0085F0_TCL1_ACTION_ENA(1) |
>  				     S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
>  		cp_coher_cntl = 0;
>  		sctx->b.num_L2_invalidates++;
>  	} else {
>  		/* L1 invalidation and L2 writeback must be done separately,
>  		 * because both operations can't be done together.
>  		 */
>  		if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
>  			/* WB = write-back
>  			 * NC = apply to non-coherent MTYPEs
>