[Mesa-dev] [PATCH 08/17] gallium/radeon: merge dirty_fb_counter and dirty_tex_descriptor_counter
Marek Olšák
maraeo at gmail.com
Thu Jan 26 16:04:24 UTC 2017
From: Marek Olšák <marek.olsak at amd.com>
to simplify things in draw_vbo a little
---
src/gallium/drivers/r600/r600_state_common.c | 8 ++++----
src/gallium/drivers/radeon/r600_pipe_common.h | 21 ++++++++-------------
src/gallium/drivers/radeon/r600_texture.c | 18 +++++-------------
src/gallium/drivers/radeonsi/si_state_draw.c | 16 +++++-----------
4 files changed, 22 insertions(+), 41 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index a9dbc8b..c8502e9 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1662,40 +1662,40 @@ void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom
}
static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct pipe_draw_info info = *dinfo;
struct pipe_index_buffer ib = {};
struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
uint64_t mask;
- unsigned num_patches, dirty_fb_counter;
+ unsigned num_patches, dirty_tex_counter;
if (!info.indirect && !info.count && (info.indexed || !info.count_from_stream_output)) {
return;
}
if (!rctx->vs_shader || !rctx->ps_shader) {
assert(0);
return;
}
/* make sure that the gfx ring is only one active */
if (radeon_emitted(rctx->b.dma.cs, 0)) {
rctx->b.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
}
/* Re-emit the framebuffer state if needed. */
- dirty_fb_counter = p_atomic_read(&rctx->b.screen->dirty_fb_counter);
- if (dirty_fb_counter != rctx->b.last_dirty_fb_counter) {
- rctx->b.last_dirty_fb_counter = dirty_fb_counter;
+ dirty_tex_counter = p_atomic_read(&rctx->b.screen->dirty_tex_counter);
+ if (dirty_tex_counter != rctx->b.last_dirty_tex_counter) {
+ rctx->b.last_dirty_tex_counter = dirty_tex_counter;
r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
}
if (!r600_update_derived_state(rctx)) {
/* useless to render because current rendering command
* can't be achieved
*/
return;
}
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index afb1385..f3e42ee 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -411,39 +411,35 @@ struct r600_common_screen {
pipe_mutex gpu_load_mutex;
pipe_thread gpu_load_thread;
union r600_grbm_counters grbm_counters;
volatile unsigned gpu_load_stop_thread; /* bool */
char renderer_string[100];
/* Performance counters. */
struct r600_perfcounters *perfcounters;
- /* If pipe_screen wants to re-emit the framebuffer state of all
- * contexts, it should atomically increment this. Each context will
- * compare this with its own last known value of the counter before
- * drawing and re-emit the framebuffer state accordingly.
+ /* If pipe_screen wants to recompute and re-emit the framebuffer,
+ * sampler, and image states of all contexts, it should atomically
+ * increment this.
+ *
+ * Each context will compare this with its own last known value of
+ * the counter before drawing and re-emit the states accordingly.
*/
- unsigned dirty_fb_counter;
+ unsigned dirty_tex_counter;
/* Atomically increment this counter when an existing texture's
* metadata is enabled or disabled in a way that requires changing
* contexts' compressed texture binding masks.
*/
unsigned compressed_colortex_counter;
- /* Atomically increment this counter when an existing texture's
- * backing buffer or tile mode parameters have changed that requires
- * recomputation of shader descriptors.
- */
- unsigned dirty_tex_descriptor_counter;
-
struct {
/* Context flags to set so that all writes from earlier jobs
* in the CP are seen by L2 clients.
*/
unsigned cp_to_L2;
/* Context flags to set so that all writes from earlier
* compute jobs are seen by L2 clients.
*/
unsigned compute_to_L2;
@@ -548,23 +544,22 @@ struct r600_common_context {
struct radeon_winsys_ctx *ctx;
enum radeon_family family;
enum chip_class chip_class;
struct r600_ring gfx;
struct r600_ring dma;
struct pipe_fence_handle *last_gfx_fence;
struct pipe_fence_handle *last_sdma_fence;
unsigned num_gfx_cs_flushes;
unsigned initial_gfx_cs_size;
unsigned gpu_reset_counter;
- unsigned last_dirty_fb_counter;
+ unsigned last_dirty_tex_counter;
unsigned last_compressed_colortex_counter;
- unsigned last_dirty_tex_descriptor_counter;
struct u_upload_mgr *uploader;
struct u_suballocator *allocator_zeroed_memory;
struct slab_child_pool pool_transfers;
/* Current unaccounted memory usage. */
uint64_t vram;
uint64_t gtt;
/* States. */
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 0b77c82..55c8e6f 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -291,25 +291,20 @@ static void r600_texture_init_metadata(struct r600_texture *rtex,
metadata->pipe_config = surface->pipe_config;
metadata->bankw = surface->bankw;
metadata->bankh = surface->bankh;
metadata->tile_split = surface->tile_split;
metadata->mtilea = surface->mtilea;
metadata->num_banks = surface->num_banks;
metadata->stride = surface->level[0].nblk_x * surface->bpe;
metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
}
-static void r600_dirty_all_framebuffer_states(struct r600_common_screen *rscreen)
-{
- p_atomic_inc(&rscreen->dirty_fb_counter);
-}
-
static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
struct r600_texture *rtex)
{
struct r600_common_screen *rscreen = rctx->screen;
struct pipe_context *ctx = &rctx->b;
if (ctx == rscreen->aux_context)
pipe_mutex_lock(rscreen->aux_context_lock);
ctx->flush_resource(ctx, &rtex->resource.b.b);
@@ -334,21 +329,21 @@ static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
if (rscreen->chip_class >= SI)
rtex->cb_color_info &= ~SI_S_028C70_FAST_CLEAR(1);
else
rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
if (rtex->cmask_buffer != &rtex->resource)
r600_resource_reference(&rtex->cmask_buffer, NULL);
/* Notify all contexts about the change. */
- r600_dirty_all_framebuffer_states(rscreen);
+ p_atomic_inc(&rscreen->dirty_tex_counter);
p_atomic_inc(&rscreen->compressed_colortex_counter);
}
static bool r600_can_disable_dcc(struct r600_texture *rtex)
{
/* We can't disable DCC if it can be written by another process. */
return rtex->dcc_offset &&
(!rtex->resource.is_shared ||
!(rtex->resource.external_usage & PIPE_HANDLE_USAGE_WRITE));
}
@@ -358,21 +353,21 @@ static bool r600_texture_discard_dcc(struct r600_common_screen *rscreen,
{
if (!r600_can_disable_dcc(rtex))
return false;
assert(rtex->dcc_separate_buffer == NULL);
/* Disable DCC. */
rtex->dcc_offset = 0;
/* Notify all contexts about the change. */
- r600_dirty_all_framebuffer_states(rscreen);
+ p_atomic_inc(&rscreen->dirty_tex_counter);
return true;
}
/**
* Disable DCC for the texture. (first decompress, then discard metadata).
*
* There is unresolved multi-context synchronization issue between
* screen::aux_context and the current context. If applications do this with
* multiple contexts, it's already undefined behavior for them and we don't
* have to worry about that. The scenario is:
@@ -473,22 +468,21 @@ static void r600_degrade_tile_mode_to_linear(struct r600_common_context *rctx,
rtex->cmask = new_tex->cmask; /* needed even without CMASK */
assert(!rtex->htile_buffer);
assert(!rtex->cmask.size);
assert(!rtex->fmask.size);
assert(!rtex->dcc_offset);
assert(!rtex->is_depth);
r600_texture_reference(&new_tex, NULL);
- r600_dirty_all_framebuffer_states(rctx->screen);
- p_atomic_inc(&rctx->screen->dirty_tex_descriptor_counter);
+ p_atomic_inc(&rctx->screen->dirty_tex_counter);
}
static boolean r600_texture_get_handle(struct pipe_screen* screen,
struct pipe_context *ctx,
struct pipe_resource *resource,
struct winsys_handle *whandle,
unsigned usage)
{
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
struct r600_common_context *rctx = (struct r600_common_context*)
@@ -1412,22 +1406,21 @@ static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
assert(!rtex->is_depth);
assert(rtex->surface.is_linear);
/* Reallocate the buffer in the same pipe_resource. */
r600_alloc_resource(rscreen, &rtex->resource);
/* Initialize the CMASK base address (needed even without CMASK). */
rtex->cmask.base_address_reg =
(rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
- r600_dirty_all_framebuffer_states(rscreen);
- p_atomic_inc(&rscreen->dirty_tex_descriptor_counter);
+ p_atomic_inc(&rscreen->dirty_tex_counter);
rctx->num_alloc_tex_transfer_bytes += rtex->size;
}
static void *r600_texture_transfer_map(struct pipe_context *ctx,
struct pipe_resource *texture,
unsigned level,
unsigned usage,
const struct pipe_box *box,
struct pipe_transfer **ptransfer)
@@ -2396,22 +2389,21 @@ static void si_set_optimal_micro_tile_mode(struct r600_common_screen *rscreen,
}
break;
default: /* depth, thick */
assert(!"unexpected micro mode");
return;
}
}
rtex->surface.micro_tile_mode = rtex->last_msaa_resolve_target_micro_mode;
- p_atomic_inc(&rscreen->dirty_fb_counter);
- p_atomic_inc(&rscreen->dirty_tex_descriptor_counter);
+ p_atomic_inc(&rscreen->dirty_tex_counter);
}
void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
struct pipe_framebuffer_state *fb,
struct r600_atom *fb_state,
unsigned *buffers, unsigned *dirty_cbufs,
const union pipe_color_union *color)
{
int i;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 0374841..c80d4d6 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -938,21 +938,21 @@ void si_ce_post_draw_synchronization(struct si_context *sctx)
sctx->ce_need_synchronization = false;
}
}
void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
{
struct si_context *sctx = (struct si_context *)ctx;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
struct pipe_index_buffer ib = {};
- unsigned mask, dirty_fb_counter, dirty_tex_counter, rast_prim;
+ unsigned mask, dirty_tex_counter, rast_prim;
if (likely(!info->indirect)) {
/* SI-CI treat instance_count==0 as instance_count==1. There is
* no workaround for indirect draws, but we can at least skip
* direct draws.
*/
if (unlikely(!info->instance_count))
return;
/* Handle count == 0. */
@@ -967,35 +967,29 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
}
if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
assert(0);
return;
}
if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
assert(0);
return;
}
- /* Re-emit the framebuffer state if needed. */
- dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
- if (unlikely(dirty_fb_counter != sctx->b.last_dirty_fb_counter)) {
- sctx->b.last_dirty_fb_counter = dirty_fb_counter;
+ /* Recompute and re-emit the texture resource states if needed. */
+ dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_counter);
+ if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_counter)) {
+ sctx->b.last_dirty_tex_counter = dirty_tex_counter;
sctx->framebuffer.dirty_cbufs |=
((1 << sctx->framebuffer.state.nr_cbufs) - 1);
sctx->framebuffer.dirty_zsbuf = true;
sctx->framebuffer.do_update_surf_dirtiness = true;
si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
- }
-
- /* Invalidate & recompute texture descriptors if needed. */
- dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_descriptor_counter);
- if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_descriptor_counter)) {
- sctx->b.last_dirty_tex_descriptor_counter = dirty_tex_counter;
si_update_all_texture_descriptors(sctx);
}
si_decompress_graphics_textures(sctx);
/* Set the rasterization primitive type.
*
* This must be done after si_decompress_textures, which can call
* draw_vbo recursively, and before si_update_shaders, which uses
* current_rast_prim for this draw_vbo call. */
--
2.7.4
More information about the mesa-dev
mailing list