[Mesa-dev] [PATCH 14/17] winsys/amdgpu: fix ADDR_REGISTER_VALUE::backendDisables

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

This would be a fix if the value was used anywhere.
---
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 08989b5..abe2b2a 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -104,21 +104,21 @@ ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
    ADDR_CREATE_FLAGS createFlags = {{0}};
    ADDR_E_RETURNCODE addrRet;
 
    addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
    addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
 
    regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
    regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
    regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
 
-   regValue.backendDisables = ws->amdinfo.backend_disable[0];
+   regValue.backendDisables = ws->amdinfo.enabled_rb_pipes_mask;
    regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
    regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
    if (ws->info.chip_class == SI) {
       regValue.pMacroTileConfig = NULL;
       regValue.noOfMacroEntries = 0;
    } else {
       regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
       regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);
    }
 
-- 
2.7.4