[Mesa-dev] [PATCH v3 03/14] i965/miptree: Replace is_lossless_compressed with mt->aux_usage checks
Jason Ekstrand
jason at jlekstrand.net
Thu Jul 13 04:23:14 UTC 2017
Now that we have an actual aux_usage field, we no longer need the
complex logic of is_lossless_compressed in order to figure out if a
miptree is CCS_E compressed. As a side-effect, there is not longer any
need to overload MSAA_LAYOUT_CMS for CCS_E and we can stop doing so.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
src/mesa/drivers/dri/i965/brw_draw.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 +--
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 39 ++++--------------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 ---
5 files changed, 10 insertions(+), 41 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 87c9dd4..1b5b0f4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -792,7 +792,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
/* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
*/
if (can_fast_clear && !irb->mt->mcs_buf) {
- assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
+ assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
/* There are a few reasons in addition to out-of-memory, that can
* cause intel_miptree_alloc_non_msrt_mcs to fail. Try to recover by
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 2ac3503..ae20e13 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -414,7 +414,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw)
if (tex_obj && tex_obj->mt) {
intel_miptree_prepare_image(brw, tex_obj->mt);
- if (intel_miptree_is_lossless_compressed(brw, tex_obj->mt) &&
+ if (tex_obj->mt->aux_usage == ISL_AUX_USAGE_CCS_E &&
intel_disable_rb_aux_buffer(brw, tex_obj->mt->bo)) {
perf_debug("Using renderbuffer as shader image - turning "
"off lossless compression");
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 3615c18..9ef5076 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -451,7 +451,7 @@ brw_texture_view_sane(const struct brw_context *brw,
const struct isl_view *view)
{
/* There are special cases only for lossless compression. */
- if (!intel_miptree_is_lossless_compressed(brw, mt))
+ if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
return true;
if (isl_format_supports_ccs_e(&brw->screen->devinfo, view->format))
@@ -493,7 +493,7 @@ brw_disable_aux_surface(const struct brw_context *brw,
view->base_array_layer, view->array_len);
/* There are special cases only for lossless compression. */
- if (!intel_miptree_is_lossless_compressed(brw, mt))
+ if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
return !is_unresolved;
const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f0b93d5..fc7b48f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -231,34 +231,6 @@ intel_miptree_supports_hiz(struct brw_context *brw,
}
}
-
-/* On Gen9 support for color buffer compression was extended to single
- * sampled surfaces. This is a helper considering both auxiliary buffer
- * type and number of samples telling if the given miptree represents
- * the new single sampled case - also called lossless compression.
- */
-bool
-intel_miptree_is_lossless_compressed(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt)
-{
- /* Only available from Gen9 onwards. */
- if (brw->gen < 9)
- return false;
-
- /* Compression always requires auxiliary buffer. */
- if (!mt->mcs_buf)
- return false;
-
- /* Single sample compression is represented re-using msaa compression
- * layout type: "Compressed Multisampled Surfaces".
- */
- if (mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS)
- return false;
-
- /* And finally distinguish between msaa and single sample case. */
- return mt->num_samples <= 1;
-}
-
static bool
intel_miptree_supports_ccs_e(struct brw_context *brw,
const struct intel_mipmap_tree *mt)
@@ -1896,7 +1868,6 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
* Software needs to initialize MCS with zeros."
*/
intel_miptree_init_mcs(brw, mt, 0);
- mt->msaa_layout = INTEL_MSAA_LAYOUT_CMS;
}
return true;
@@ -2195,10 +2166,11 @@ intel_miptree_prepare_ccs_access(struct brw_context *brw,
enum isl_aux_state aux_state = intel_miptree_get_aux_state(mt, level, layer);
enum blorp_fast_clear_op resolve_op;
- if (intel_miptree_is_lossless_compressed(brw, mt)) {
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
resolve_op = get_ccs_e_resolve_op(aux_state, aux_supported,
fast_clear_supported);
} else {
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_D);
resolve_op = get_ccs_d_resolve_op(aux_state, aux_supported,
fast_clear_supported);
}
@@ -2236,7 +2208,7 @@ intel_miptree_finish_ccs_write(struct brw_context *brw,
{
enum isl_aux_state aux_state = intel_miptree_get_aux_state(mt, level, layer);
- if (intel_miptree_is_lossless_compressed(brw, mt)) {
+ if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
switch (aux_state) {
case ISL_AUX_STATE_CLEAR:
assert(written_with_ccs);
@@ -2263,6 +2235,7 @@ intel_miptree_finish_ccs_write(struct brw_context *brw,
unreachable("Invalid aux state for CCS_E");
}
} else {
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_D);
/* CCS_D is a bit simpler */
switch (aux_state) {
case ISL_AUX_STATE_CLEAR:
@@ -2584,7 +2557,7 @@ can_texture_with_ccs(struct brw_context *brw,
struct intel_mipmap_tree *mt,
mesa_format view_format)
{
- if (!intel_miptree_is_lossless_compressed(brw, mt))
+ if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
return false;
enum isl_format isl_mt_format = brw_isl_format_for_mesa_format(mt->format);
@@ -2684,7 +2657,7 @@ intel_miptree_prepare_render(struct brw_context *brw,
/* Lossless compression is not supported for SRGB formats, it
* should be impossible to get here with such surfaces.
*/
- assert(!intel_miptree_is_lossless_compressed(brw, mt));
+ assert(mt->aux_usage != ISL_AUX_USAGE_CCS_E);
intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
false, false);
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index c4ed525..cc896fc 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -642,10 +642,6 @@ struct intel_mipmap_tree
};
bool
-intel_miptree_is_lossless_compressed(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt);
-
-bool
intel_miptree_alloc_ccs(struct brw_context *brw,
struct intel_mipmap_tree *mt);
--
2.5.0.400.gff86faf
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