[Mesa-dev] [PATCH 04/22] i965/miptree: Switch to isl_surf::row_pitch
Jason Ekstrand
jason at jlekstrand.net
Tue Jul 18 20:45:53 UTC 2017
On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolainen at gmail.com> wrote:
> Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_misc_state.c | 2 +-
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +-
> src/mesa/drivers/dri/i965/gen6_depth_state.c | 2 +-
> src/mesa/drivers/dri/i965/gen7_misc_state.c | 4 +-
> src/mesa/drivers/dri/i965/gen8_depth_state.c | 4 +-
> src/mesa/drivers/dri/i965/intel_blit.c | 13 +++---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 54
> +++++++++++++-----------
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 11 -----
> src/mesa/drivers/dri/i965/intel_pixel_bitmap.c | 2 +-
> src/mesa/drivers/dri/i965/intel_pixel_read.c | 2 +-
> src/mesa/drivers/dri/i965/intel_screen.c | 4 +-
> src/mesa/drivers/dri/i965/intel_tex_image.c | 8 ++--
> src/mesa/drivers/dri/i965/intel_tex_subimage.c | 2 +-
> 13 files changed, 52 insertions(+), 58 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
> b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index b0e63347ad..0c43d2b4b2 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -380,7 +380,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
>
> BEGIN_BATCH(len);
> OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
> - OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
> + OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
> (depthbuffer_format << 18) |
> (BRW_TILEWALK_YMAJOR << 26) |
> ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 5e4b4d626e..ab6b9cdd29 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -1034,7 +1034,7 @@ gen4_update_renderbuffer_surface(struct brw_context
> *brw,
> (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
>
> surf[3] = (brw_get_surface_tiling_bits(mt->surf.tiling) |
> - (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
> + (mt->surf.row_pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
>
> surf[4] = brw_get_surface_num_multisamples(mt->surf.samples);
>
> diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> index e042fc747e..8f05b4cc1a 100644
> --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> @@ -116,7 +116,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
> OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
>
> /* 3DSTATE_DEPTH_BUFFER dw1 */
> - OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
> + OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
> (depthbuffer_format << 18) |
> ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable
> */
> ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
> diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> index 6c69fa8ba5..43422900e2 100644
> --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> @@ -105,7 +105,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
> OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
>
> /* 3DSTATE_DEPTH_BUFFER dw1 */
> - OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
> + OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
> (depthbuffer_format << 18) |
> ((hiz ? 1 : 0) << 22) |
> ((stencil_mt != NULL && brw->stencil_write_enabled) << 27) |
> @@ -182,7 +182,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
> */
> OUT_BATCH(enabled |
> mocs << 25 |
> - (2 * stencil_mt->pitch - 1));
> + (2 * stencil_mt->surf.row_pitch - 1));
>
As with other patches, is the objective simply to switch fields or are we
also switching to the semantics of the ISL field? If we're also switching
semantics (which is what I'd do personally), then this shouldn't be *2
anymore. Looking through this patch, you appear to have a mix of ISL and
miptree semantics.
> OUT_RELOC(stencil_mt->bo,
> I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> 0);
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index 52c6dd0787..9cb0d07688 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -67,7 +67,7 @@ emit_depth_packets(struct brw_context *brw,
> (stencil_mt != NULL && stencil_writable) << 27 |
> (hiz ? 1 : 0) << 22 |
> depthbuffer_format << 18 |
> - (depth_mt ? depth_mt->pitch - 1 : 0));
> + (depth_mt ? depth_mt->surf.row_pitch - 1 : 0));
> if (depth_mt) {
> OUT_RELOC64(depth_mt->bo,
> I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
> @@ -126,7 +126,7 @@ emit_depth_packets(struct brw_context *brw,
> * indicate that it does.
> */
> OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
> - (2 * stencil_mt->pitch - 1));
> + (2 * stencil_mt->surf.row_pitch - 1));
>
And here.
> OUT_RELOC64(stencil_mt->bo,
> I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
> OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
> diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
> b/src/mesa/drivers/dri/i965/intel_blit.c
> index 58124043fa..a6f7aee32f 100644
> --- a/src/mesa/drivers/dri/i965/intel_blit.c
> +++ b/src/mesa/drivers/dri/i965/intel_blit.c
> @@ -131,7 +131,7 @@ set_blitter_tiling(struct brw_context *brw,
> static int
> blt_pitch(struct intel_mipmap_tree *mt)
> {
> - int pitch = mt->pitch;
> + int pitch = mt->surf.row_pitch;
> if (mt->surf.tiling != ISL_TILING_LINEAR)
> pitch /= 4;
> return pitch;
> @@ -172,7 +172,7 @@ get_blit_intratile_offset_el(const struct brw_context
> *brw,
> uint32_t *y_offset_el)
> {
> enum isl_tiling tiling = intel_miptree_get_isl_tiling(mt);
> - isl_tiling_get_intratile_offset_el(tiling, mt->cpp * 8, mt->pitch,
> + isl_tiling_get_intratile_offset_el(tiling, mt->cpp * 8,
> mt->surf.row_pitch,
> total_x_offset_el,
> total_y_offset_el,
> base_address_offset,
> x_offset_el, y_offset_el);
> @@ -187,7 +187,7 @@ get_blit_intratile_offset_el(const struct brw_context
> *brw,
> * The offsets we get from ISL in the tiled case are already
> aligned.
> * In the linear case, we need to do some of our own aligning.
> */
> - assert(mt->pitch % 64 == 0);
> + assert(mt->surf.row_pitch % 64 == 0);
> uint32_t delta = *base_address_offset & 63;
> assert(delta % mt->cpp == 0);
> *base_address_offset -= delta;
> @@ -251,10 +251,11 @@ emit_miptree_blit(struct brw_context *brw,
>
> if (!intelEmitCopyBlit(brw,
> src_mt->cpp,
> - reverse ? -src_mt->pitch : src_mt->pitch,
> + reverse ? -src_mt->surf.row_pitch :
> + src_mt->surf.row_pitch,
> src_mt->bo, src_mt->offset + src_offset,
> src_mt->surf.tiling,
> - dst_mt->pitch,
> + dst_mt->surf.row_pitch,
> dst_mt->bo, dst_mt->offset + dst_offset,
> dst_mt->surf.tiling,
> src_tile_x, src_tile_y,
> @@ -772,7 +773,7 @@ intel_miptree_set_alpha_to_one(struct brw_context
> *brw,
> uint32_t BR13, CMD;
> int pitch, cpp;
>
> - pitch = mt->pitch;
> + pitch = mt->surf.row_pitch;
> cpp = mt->cpp;
>
> DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 1dcf6d5d84..f113ded7cd 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -854,7 +854,7 @@ miptree_create(struct brw_context *brw,
> mt->cpp,
> isl_tiling_to_bufmgr_tiling(
> mt->surf.tiling),
> - &mt->pitch,
> + &mt->surf.row_pitch,
> alloc_flags);
> } else {
> mt->bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "miptree",
> @@ -862,7 +862,7 @@ miptree_create(struct brw_context *brw,
> mt->cpp,
> isl_tiling_to_bufmgr_tiling(
> mt->surf.tiling),
> - &mt->pitch,
> + &mt->surf.row_pitch,
> alloc_flags);
> }
>
> @@ -913,7 +913,7 @@ intel_miptree_create(struct brw_context *brw,
> mt->total_width, mt->total_height,
> mt->cpp,
> isl_tiling_to_bufmgr_tiling(
> mt->surf.tiling),
> - &mt->pitch, alloc_flags);
> + &mt->surf.row_pitch, alloc_flags);
> }
>
> mt->offset = 0;
> @@ -991,7 +991,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
>
> brw_bo_reference(bo);
> mt->bo = bo;
> - mt->pitch = pitch;
> + mt->surf.row_pitch = pitch;
> mt->offset = offset;
> mt->surf.tiling = bufmgr_tiling_to_isl_tiling(tiling);
>
> @@ -1515,7 +1515,7 @@ intel_miptree_get_aligned_offset(const struct
> intel_mipmap_tree *mt,
> uint32_t x, uint32_t y)
> {
> int cpp = mt->cpp;
> - uint32_t pitch = mt->pitch;
> + uint32_t pitch = mt->surf.row_pitch;
>
> switch (mt->surf.tiling) {
> default:
> @@ -1684,9 +1684,9 @@ intel_miptree_copy_slice(struct brw_context *brw,
>
> DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
> _mesa_get_format_name(src_mt->format),
> - src_mt, src_x, src_y, src_mt->pitch,
> + src_mt, src_x, src_y, src_mt->surf.row_pitch,
> _mesa_get_format_name(dst_mt->format),
> - dst_mt, dst_x, dst_y, dst_mt->pitch,
> + dst_mt, dst_x, dst_y, dst_mt->surf.row_pitch,
> width, height);
>
> if (!intel_miptree_blit(brw,
> @@ -3010,7 +3010,7 @@ intel_miptree_map_gtt(struct brw_context *brw,
> x += image_x;
> y += image_y;
>
> - map->stride = mt->pitch;
> + map->stride = mt->surf.row_pitch;
> map->ptr = base + y * map->stride + x * mt->cpp;
> }
>
> @@ -3044,7 +3044,7 @@ intel_miptree_map_blit(struct brw_context *brw,
> fprintf(stderr, "Failed to allocate blit temporary\n");
> goto fail;
> }
> - map->stride = map->linear_mt->pitch;
> + map->stride = map->linear_mt->surf.row_pitch;
>
> /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT
> implies no
> * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in
> unless
> @@ -3129,7 +3129,7 @@ intel_miptree_map_movntdqa(struct brw_context *brw,
>
> src += mt->offset;
>
> - src += image_y * mt->pitch;
> + src += image_y * mt->surf.row_pitch;
> src += image_x * mt->cpp;
>
> /* Due to the pixel offsets for the particular image being mapped, our
> @@ -3137,7 +3137,7 @@ intel_miptree_map_movntdqa(struct brw_context *brw,
> * divisible by 16, then the amount by which it's misaligned will
> remain
> * consistent from row to row.
> */
> - assert((mt->pitch % 16) == 0);
> + assert((mt->surf.row_pitch % 16) == 0);
> const int misalignment = ((uintptr_t) src) & 15;
>
> /* Create an untiled temporary buffer for the mapping. */
> @@ -3153,7 +3153,7 @@ intel_miptree_map_movntdqa(struct brw_context *brw,
>
> for (uint32_t y = 0; y < map->h; y++) {
> void *dst_ptr = map->ptr + y * map->stride;
> - void *src_ptr = src + y * mt->pitch;
> + void *src_ptr = src + y * mt->surf.row_pitch;
>
> _mesa_streaming_load_memcpy(dst_ptr, src_ptr, width_bytes);
> }
> @@ -3196,7 +3196,8 @@ intel_miptree_map_s8(struct brw_context *brw,
> * to intel_offset_S8() which expects the legacy interpretation.
> */
> const unsigned pitch = mt->surf.size > 0 ?
> - mt->surf.row_pitch / 2 : mt->pitch;
> + mt->surf.row_pitch / 2 :
>
This is consistent with the ISL semantics.
> + mt->surf.row_pitch;
> uint8_t *untiled_s8_map = map->ptr;
> uint8_t *tiled_s8_map = intel_miptree_map_raw(brw, mt,
> GL_MAP_READ_BIT);
> unsigned int image_x, image_y;
> @@ -3238,7 +3239,8 @@ intel_miptree_unmap_s8(struct brw_context *brw,
> * to intel_offset_S8() which expects the legacy interpretation.
> */
> const unsigned pitch = mt->surf.size > 0 ?
> - mt->surf.row_pitch / 2: mt->pitch;
> + mt->surf.row_pitch / 2 :
>
And so is this.
> + mt->surf.row_pitch;
> unsigned int image_x, image_y;
> uint8_t *untiled_s8_map = map->ptr;
> uint8_t *tiled_s8_map = intel_miptree_map_raw(brw, mt,
> GL_MAP_WRITE_BIT);
> @@ -3297,15 +3299,15 @@ intel_miptree_unmap_etc(struct brw_context *brw,
> image_y += map->y;
>
> uint8_t *dst = intel_miptree_map_raw(brw, mt, GL_MAP_WRITE_BIT)
> - + image_y * mt->pitch
> + + image_y * mt->surf.row_pitch
> + image_x * mt->cpp;
>
> if (mt->etc_format == MESA_FORMAT_ETC1_RGB8)
> - _mesa_etc1_unpack_rgba8888(dst, mt->pitch,
> + _mesa_etc1_unpack_rgba8888(dst, mt->surf.row_pitch,
> map->ptr, map->stride,
> map->w, map->h);
> else
> - _mesa_unpack_etc2_format(dst, mt->pitch,
> + _mesa_unpack_etc2_format(dst, mt->surf.row_pitch,
> map->ptr, map->stride,
> map->w, map->h, mt->etc_format);
>
> @@ -3351,7 +3353,8 @@ intel_miptree_map_depthstencil(struct brw_context
> *brw,
> * to intel_offset_S8() which expects the legacy interpretation.
> */
> const unsigned s_pitch = s_mt->surf.size > 0 ?
> - s_mt->surf.row_pitch / 2 : s_mt->pitch;
> + s_mt->surf.row_pitch / 2 :
> + s_mt->surf.row_pitch;
>
This doesn't use ISL semantics
> uint32_t *packed_map = map->ptr;
> uint8_t *s_map = intel_miptree_map_raw(brw, s_mt, GL_MAP_READ_BIT);
> uint32_t *z_map = intel_miptree_map_raw(brw, z_mt, GL_MAP_READ_BIT);
> @@ -3371,7 +3374,7 @@ intel_miptree_map_depthstencil(struct brw_context
> *brw,
> map_y + s_image_y,
> brw->has_swizzling);
> ptrdiff_t z_offset = ((map_y + z_image_y) *
> - (z_mt->pitch / 4) +
> + (z_mt->surf.row_pitch / 4) +
> (map_x + z_image_x));
> uint8_t s = s_map[s_offset];
> uint32_t z = z_map[z_offset];
> @@ -3418,7 +3421,8 @@ intel_miptree_unmap_depthstencil(struct brw_context
> *brw,
> * to intel_offset_S8() which expects the legacy interpretation.
> */
> const unsigned s_pitch = s_mt->surf.size > 0 ?
> - s_mt->surf.row_pitch / 2 : s_mt->pitch;
> + s_mt->surf.row_pitch / 2 :
> + s_mt->surf.row_pitch;
>
Neither does this.
> uint32_t *packed_map = map->ptr;
> uint8_t *s_map = intel_miptree_map_raw(brw, s_mt, GL_MAP_WRITE_BIT);
> uint32_t *z_map = intel_miptree_map_raw(brw, z_mt,
> GL_MAP_WRITE_BIT);
> @@ -3437,7 +3441,7 @@ intel_miptree_unmap_depthstencil(struct brw_context
> *brw,
> y + s_image_y + map->y,
> brw->has_swizzling);
> ptrdiff_t z_offset = ((y + z_image_y + map->y) *
> - (z_mt->pitch / 4) +
> + (z_mt->surf.row_pitch / 4) +
> (x + z_image_x + map->x));
>
> if (map_z32f_x24s8) {
> @@ -3517,7 +3521,7 @@ can_blit_slice(struct intel_mipmap_tree *mt,
> unsigned int level, unsigned int slice)
> {
> /* See intel_miptree_blit() for details on the 32k pitch limit. */
> - if (mt->pitch >= 32768)
> + if (mt->surf.row_pitch >= 32768)
> return false;
>
> return true;
> @@ -3603,7 +3607,7 @@ intel_miptree_map(struct brw_context *brw,
> #if defined(USE_SSE41)
> } else if (!(mode & GL_MAP_WRITE_BIT) &&
> !mt->compressed && cpu_has_sse4_1 &&
> - (mt->pitch % 16 == 0)) {
> + (mt->surf.row_pitch % 16 == 0)) {
> intel_miptree_map_movntdqa(brw, mt, map, level, slice);
> #endif
> } else {
> @@ -3738,9 +3742,9 @@ intel_miptree_get_isl_surf(struct brw_context *brw,
> * a bit better than intel_mipmap_tree. In particular, ISL
> incorporates
> * the factor of 2 for W-tiling in row_pitch.
> */
> - surf->row_pitch = 2 * mt->pitch;
> + surf->row_pitch = 2 * mt->surf.row_pitch;
> } else {
> - surf->row_pitch = mt->pitch;
> + surf->row_pitch = mt->surf.row_pitch;
> }
>
> surf->format = translate_tex_format(brw, mt->format, false);
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index bc4095997d..e7872ff96c 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -320,17 +320,6 @@ struct intel_mipmap_tree
> struct brw_bo *bo;
>
> /**
> - * Pitch in bytes.
> - *
> - * @see RENDER_SURFACE_STATE.SurfacePitch
> - * @see RENDER_SURFACE_STATE.AuxiliarySurfacePitch
> - * @see 3DSTATE_DEPTH_BUFFER.SurfacePitch
> - * @see 3DSTATE_HIER_DEPTH_BUFFER.SurfacePitch
> - * @see 3DSTATE_STENCIL_BUFFER.SurfacePitch
> - */
> - uint32_t pitch;
> -
> - /**
> * @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
> *
> * @see RENDER_SURFACE_STATE.SurfaceType
> diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
> b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
> index 47d7b6933d..aeea3c8bd6 100644
> --- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
> +++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
> @@ -292,7 +292,7 @@ do_blit_bitmap( struct gl_context *ctx,
> (GLubyte *)stipple,
> sz,
> color,
> - irb->mt->pitch,
> + irb->mt->surf.row_pitch,
> irb->mt->bo,
> 0,
> irb->mt->surf.tiling,
> diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c
> b/src/mesa/drivers/dri/i965/intel_pixel_read.c
> index aa228ce721..cd4fbab097 100644
> --- a/src/mesa/drivers/dri/i965/intel_pixel_read.c
> +++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
> @@ -201,7 +201,7 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx,
> yoffset, yoffset + height,
> pixels - (ptrdiff_t) yoffset * dst_pitch - (ptrdiff_t) xoffset *
> cpp,
> map + irb->mt->offset,
> - dst_pitch, irb->mt->pitch,
> + dst_pitch, irb->mt->surf.row_pitch,
> brw->has_swizzling,
> irb->mt->surf.tiling,
> mem_copy
> diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
> b/src/mesa/drivers/dri/i965/intel_screen.c
> index 4a89037904..7a92ef601b 100644
> --- a/src/mesa/drivers/dri/i965/intel_screen.c
> +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> @@ -414,7 +414,7 @@ intel_setup_image_from_mipmap_tree(struct brw_context
> *brw, __DRIimage *image,
>
> image->width = minify(mt->physical_width0, level - mt->first_level);
> image->height = minify(mt->physical_height0, level - mt->first_level);
> - image->pitch = mt->pitch;
> + image->pitch = mt->surf.row_pitch;
>
> image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,
> &image->tile_x,
> @@ -490,7 +490,7 @@ intel_create_image_from_renderbuffer(__DRIcontext
> *context,
> brw_bo_reference(irb->mt->bo);
> image->width = rb->Width;
> image->height = rb->Height;
> - image->pitch = irb->mt->pitch;
> + image->pitch = irb->mt->surf.row_pitch;
> image->dri_format = driGLFormatToImageFormat(image->format);
> image->has_depthstencil = irb->mt->stencil_mt? true : false;
>
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
> b/src/mesa/drivers/dri/i965/intel_tex_image.c
> index 504868465c..2db5a34655 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_image.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
> @@ -205,8 +205,8 @@ intel_set_texture_image_mt(struct brw_context *brw,
> brw->ctx.Driver.FreeTextureImageBuffer(&brw->ctx, image);
>
> intel_texobj->needs_validate = true;
> - intel_image->base.RowStride = mt->pitch / mt->cpp;
> - assert(mt->pitch % mt->cpp == 0);
> + intel_image->base.RowStride = mt->surf.row_pitch / mt->cpp;
> + assert(mt->surf.row_pitch % mt->cpp == 0);
>
> intel_miptree_reference(&intel_image->mt, mt);
>
> @@ -264,7 +264,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint
> target,
> mt = intel_miptree_create_for_bo(brw, rb->mt->bo, texFormat, 0,
> rb->Base.Base.Width,
> rb->Base.Base.Height,
> - 1, rb->mt->pitch, 0);
> + 1, rb->mt->surf.row_pitch, 0);
> if (mt == NULL)
> return;
> mt->target = target;
> @@ -492,7 +492,7 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context
> *ctx,
> yoffset, yoffset + height,
> pixels - (ptrdiff_t) yoffset * dst_pitch - (ptrdiff_t) xoffset *
> cpp,
> map,
> - dst_pitch, image->mt->pitch,
> + dst_pitch, image->mt->surf.row_pitch,
> brw->has_swizzling,
> image->mt->surf.tiling,
> mem_copy
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
> b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
> index 52a5d39812..e686ba93d2 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
> @@ -191,7 +191,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context *
> ctx,
> yoffset, yoffset + height,
> map,
> pixels - (ptrdiff_t) yoffset * src_pitch - (ptrdiff_t) xoffset *
> cpp,
> - image->mt->pitch, src_pitch,
> + image->mt->surf.row_pitch, src_pitch,
> brw->has_swizzling,
> image->mt->surf.tiling,
> mem_copy
> --
> 2.11.0
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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