[Mesa-dev] [PATCH 04/22] i965/miptree: Switch to isl_surf::row_pitch

[Pohjolainen, Topi]

On Tue, Jul 18, 2017 at 01:45:53PM -0700, Jason Ekstrand wrote:
> On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
> topi.pohjolainen at gmail.com> wrote:
> 
> > Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> > ---
> >  src/mesa/drivers/dri/i965/brw_misc_state.c       |  2 +-
> >  src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  2 +-
> >  src/mesa/drivers/dri/i965/gen6_depth_state.c     |  2 +-
> >  src/mesa/drivers/dri/i965/gen7_misc_state.c      |  4 +-
> >  src/mesa/drivers/dri/i965/gen8_depth_state.c     |  4 +-
> >  src/mesa/drivers/dri/i965/intel_blit.c           | 13 +++---
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c    | 54
> > +++++++++++++-----------
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.h    | 11 -----
> >  src/mesa/drivers/dri/i965/intel_pixel_bitmap.c   |  2 +-
> >  src/mesa/drivers/dri/i965/intel_pixel_read.c     |  2 +-
> >  src/mesa/drivers/dri/i965/intel_screen.c         |  4 +-
> >  src/mesa/drivers/dri/i965/intel_tex_image.c      |  8 ++--
> >  src/mesa/drivers/dri/i965/intel_tex_subimage.c   |  2 +-
> >  13 files changed, 52 insertions(+), 58 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
> > b/src/mesa/drivers/dri/i965/brw_misc_state.c
> > index b0e63347ad..0c43d2b4b2 100644
> > --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> > +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> > @@ -380,7 +380,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
> >
> >     BEGIN_BATCH(len);
> >     OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
> > -   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
> > +   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
> >               (depthbuffer_format << 18) |
> >               (BRW_TILEWALK_YMAJOR << 26) |
> >               ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)
> > diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > index 5e4b4d626e..ab6b9cdd29 100644
> > --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > @@ -1034,7 +1034,7 @@ gen4_update_renderbuffer_surface(struct brw_context
> > *brw,
> >               (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
> >
> >     surf[3] = (brw_get_surface_tiling_bits(mt->surf.tiling) |
> > -             (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
> > +             (mt->surf.row_pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
> >
> >     surf[4] = brw_get_surface_num_multisamples(mt->surf.samples);
> >
> > diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> > b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> > index e042fc747e..8f05b4cc1a 100644
> > --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> > @@ -116,7 +116,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
> >     OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
> >
> >     /* 3DSTATE_DEPTH_BUFFER dw1 */
> > -   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
> > +   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
> >               (depthbuffer_format << 18) |
> >               ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable
> > */
> >               ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
> > diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> > b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> > index 6c69fa8ba5..43422900e2 100644
> > --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> > @@ -105,7 +105,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
> >     OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
> >
> >     /* 3DSTATE_DEPTH_BUFFER dw1 */
> > -   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
> > +   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
> >               (depthbuffer_format << 18) |
> >               ((hiz ? 1 : 0) << 22) |
> >               ((stencil_mt != NULL && brw->stencil_write_enabled) << 27) |
> > @@ -182,7 +182,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
> >         */
> >        OUT_BATCH(enabled |
> >                  mocs << 25 |
> > -               (2 * stencil_mt->pitch - 1));
> > +               (2 * stencil_mt->surf.row_pitch - 1));
> >
> 
> As with other patches, is the objective simply to switch fields or are we
> also switching to the semantics of the ISL field?  If we're also switching
> semantics (which is what I'd do personally), then this shouldn't be *2
> anymore.  Looking through this patch, you appear to have a mix of ISL and
> miptree semantics.

I agree, this is confusing. I wrote another patch to precede this patch that
starts to use interleaved stencil pitch even for the native miptree. Sending
shortly once I'm done with rebasing and testing.