[Mesa-dev] [1.5/22] i965/miptree: Use num_samples of 1 instead of 0 for single-sampled
Topi Pohjolainen
topi.pohjolainen at gmail.com
Wed Jul 19 19:43:54 UTC 2017
Patch moves "assert(brw->num_samples <= 16)" from
emit_3dstate_multisample2() to upload_multisample_state(). Latter
is the only caller of the former and passes "brw->num_samples"
as argument. Therefore it is clearer to assert in the caller.
Possible bug fix in genX(emit_3dstate_multisample2) which
doesn't have a case for num_samples == 0 in the switch
statement.
It should be noted that intel_miptree_map()/unmap() now checks
additionally for "mt->surf.samples == 1" in order to support gen6
stencil which is already transitioned to ISL. This will go away in
next patch when native miptrees start to use isl_surf::samples as
well.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
src/mesa/drivers/dri/i965/brw_context.c | 2 +-
src/mesa/drivers/dri/i965/brw_meta_util.c | 2 +-
src/mesa/drivers/dri/i965/brw_state_upload.c | 3 +-
src/mesa/drivers/dri/i965/genX_state_upload.c | 6 ++--
src/mesa/drivers/dri/i965/intel_fbo.c | 7 ++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 40 +++++++++++++++-----------
src/mesa/drivers/dri/i965/intel_tex.c | 4 +--
src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +-
src/mesa/drivers/dri/i965/intel_tex_validate.c | 2 +-
10 files changed, 38 insertions(+), 32 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index be310de85b..2776872d92 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -135,7 +135,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
struct isl_surf tmp_surfs[1])
{
if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
- const unsigned num_samples = MAX2(1, mt->num_samples);
+ const unsigned num_samples = mt->num_samples;
for (unsigned i = 0; i < num_layers; i++) {
for (unsigned s = 0; s < num_samples; s++) {
const unsigned phys_layer = (start_layer + i) * num_samples + s;
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index bd26e2332c..303c658543 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1218,7 +1218,7 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
rb = intel_get_renderbuffer(fb, buffers[i]);
if (rb == NULL || rb->mt == NULL)
continue;
- if (rb->mt->num_samples <= 1) {
+ if (rb->mt->num_samples == 1) {
assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
rb->layer_count == 1);
intel_miptree_prepare_access(brw, rb->mt, 0, 1, 0, 1, false, false);
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c b/src/mesa/drivers/dri/i965/brw_meta_util.c
index f9fd350918..7b5a11811b 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -298,7 +298,7 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw,
* fast clear because it's very likely to be immediately resolved.
*/
if (brw->gen >= 9 &&
- mt->num_samples <= 1 &&
+ mt->num_samples == 1 &&
ctx->Color.sRGBEnabled &&
_mesa_get_srgb_format_linear(mt->format) != mt->format)
return false;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 8ee2dff072..acaa97ee7d 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -457,7 +457,8 @@ brw_upload_pipeline_state(struct brw_context *brw,
int i;
static int dirty_count = 0;
struct brw_state_flags state = brw->state.pipelines[pipeline];
- unsigned int fb_samples = _mesa_geometric_samples(ctx->DrawBuffer);
+ const unsigned fb_samples =
+ MAX2(_mesa_geometric_samples(ctx->DrawBuffer), 1);
brw_select_pipeline(brw, pipeline);
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 64bcc2fd0d..ef04603df8 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -3287,9 +3287,7 @@ static void
genX(emit_3dstate_multisample2)(struct brw_context *brw,
unsigned num_samples)
{
- assert(brw->num_samples <= 16);
-
- unsigned log2_samples = ffs(MAX2(num_samples, 1)) - 1;
+ unsigned log2_samples = ffs(num_samples) - 1;
brw_batch_emit(brw, GENX(3DSTATE_MULTISAMPLE), multi) {
multi.PixelLocation = CENTER;
@@ -3320,6 +3318,8 @@ genX(emit_3dstate_multisample2)(struct brw_context *brw,
static void
genX(upload_multisample_state)(struct brw_context *brw)
{
+ assert(brw->num_samples > 0 && brw->num_samples <= 16);
+
genX(emit_3dstate_multisample2)(brw, brw->num_samples);
brw_batch_emit(brw, GENX(3DSTATE_SAMPLE_MASK), sm) {
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 3ac6892ea0..b7de49f22e 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -143,7 +143,7 @@ intel_map_renderbuffer(struct gl_context *ctx,
irb->singlesample_mt =
intel_miptree_create_for_renderbuffer(brw, irb->mt->format,
rb->Width, rb->Height,
- 0 /*num_samples*/);
+ 1 /*num_samples*/);
if (!irb->singlesample_mt)
goto fail;
irb->singlesample_mt_is_tmp = true;
@@ -303,7 +303,7 @@ intel_alloc_private_renderbuffer_storage(struct gl_context * ctx, struct gl_rend
irb->mt = intel_miptree_create_for_renderbuffer(brw, rb->Format,
width, height,
- rb->NumSamples);
+ MAX2(rb->NumSamples, 1));
if (!irb->mt)
return false;
@@ -533,8 +533,7 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
irb->mt_layer = layer;
const unsigned layer_multiplier =
- mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY ?
- MAX2(mt->num_samples, 1) : 1;
+ mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY ? mt->num_samples : 1;
if (!layered) {
irb->layer_count = 1;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 8e241b8462..338e965737 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -191,7 +191,7 @@ intel_miptree_supports_ccs(struct brw_context *brw,
* accidentally reject a multisampled surface here. We should have
* rejected it earlier by explicitly checking the sample count.
*/
- assert(mt->num_samples <= 1);
+ assert(mt->num_samples == 1);
}
/* Handle the hardware restrictions...
@@ -358,6 +358,8 @@ intel_miptree_create_layout(struct brw_context *brw,
GLuint num_samples,
uint32_t layout_flags)
{
+ assert(num_samples > 0);
+
struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
if (!mt)
return NULL;
@@ -568,7 +570,7 @@ intel_miptree_create_layout(struct brw_context *brw,
* 6 | ? | ?
*/
if (intel_miptree_supports_ccs(brw, mt)) {
- if (brw->gen >= 9 || (brw->gen == 8 && num_samples <= 1))
+ if (brw->gen >= 9 || (brw->gen == 8 && num_samples == 1))
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
} else if (brw->gen >= 9 && num_samples > 1) {
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
@@ -766,7 +768,7 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format,
.depth = target == GL_TEXTURE_3D ? depth0 : 1,
.levels = last_level - first_level + 1,
.array_len = target == GL_TEXTURE_3D ? 1 : depth0,
- .samples = MAX2(num_samples, 1),
+ .samples = num_samples,
.row_pitch = row_pitch,
.usage = isl_usage_flags,
.tiling_flags = tiling_flags,
@@ -882,6 +884,8 @@ intel_miptree_create(struct brw_context *brw,
GLuint num_samples,
uint32_t layout_flags)
{
+ assert(num_samples > 0);
+
struct intel_mipmap_tree *mt = miptree_create(
brw, target, format,
first_level, last_level,
@@ -977,7 +981,8 @@ intel_miptree_create_for_bo(struct brw_context *brw,
layout_flags |= MIPTREE_LAYOUT_FOR_BO;
mt = intel_miptree_create_layout(brw, target, format,
0, 0,
- width, height, depth, 0,
+ width, height, depth,
+ 1 /* num_samples */,
layout_flags);
if (!mt)
return NULL;
@@ -1150,7 +1155,7 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
struct intel_mipmap_tree *multisample_mt = NULL;
struct gl_renderbuffer *rb = &irb->Base.Base;
mesa_format format = rb->Format;
- int num_samples = rb->NumSamples;
+ const unsigned num_samples = MAX2(rb->NumSamples, 1);
/* Only the front and back buffers, which are color buffers, are allocated
* through the image loader.
@@ -1160,7 +1165,7 @@ intel_update_winsys_renderbuffer_miptree(struct brw_context *intel,
assert(singlesample_mt);
- if (num_samples == 0) {
+ if (num_samples == 1) {
intel_miptree_release(&irb->mt);
irb->mt = singlesample_mt;
@@ -1377,7 +1382,8 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt,
return false;
}
- if (image->NumSamples != mt->num_samples)
+ /* Core uses sample number of zero to indicate single-sampled. */
+ if (MAX2(image->NumSamples, 1) != mt->num_samples)
return false;
return true;
@@ -2011,7 +2017,7 @@ intel_miptree_alloc_aux(struct brw_context *brw,
case ISL_AUX_USAGE_CCS_E:
assert(_mesa_is_format_color_format(mt->format));
- assert(mt->num_samples <= 1);
+ assert(mt->num_samples == 1);
if (!intel_miptree_alloc_ccs(brw, mt))
return false;
return true;
@@ -2060,7 +2066,7 @@ intel_miptree_sample_with_hiz(struct brw_context *brw,
* There is no such blurb for 1D textures, but there is sufficient evidence
* that this is broken on SKL+.
*/
- return (mt->num_samples <= 1 &&
+ return (mt->num_samples == 1 &&
mt->target != GL_TEXTURE_3D &&
mt->target != GL_TEXTURE_1D /* gen9+ restriction */);
}
@@ -2541,7 +2547,7 @@ intel_miptree_get_aux_state(const struct intel_mipmap_tree *mt,
if (_mesa_is_format_color_format(mt->format)) {
assert(mt->mcs_buf != NULL);
- assert(mt->num_samples <= 1 ||
+ assert(mt->num_samples == 1 ||
mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
} else if (mt->format == MESA_FORMAT_S_UINT8) {
unreachable("Cannot get aux state for stencil");
@@ -2562,7 +2568,7 @@ intel_miptree_set_aux_state(struct brw_context *brw,
if (_mesa_is_format_color_format(mt->format)) {
assert(mt->mcs_buf != NULL);
- assert(mt->num_samples <= 1 ||
+ assert(mt->num_samples == 1 ||
mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
} else if (mt->format == MESA_FORMAT_S_UINT8) {
unreachable("Cannot get aux state for stencil");
@@ -2684,7 +2690,7 @@ intel_miptree_prepare_render(struct brw_context *brw,
* enabled because otherwise the surface state will be programmed with
* the linear equivalent format anyway.
*/
- if (brw->gen == 9 && srgb_enabled && mt->num_samples <= 1 &&
+ if (brw->gen == 9 && srgb_enabled && mt->num_samples == 1 &&
_mesa_get_srgb_format_linear(mt->format) != mt->format) {
/* Lossless compression is not supported for SRGB formats, it
@@ -2747,7 +2753,7 @@ intel_miptree_make_shareable(struct brw_context *brw,
* reached for multisample buffers.
*/
assert(mt->surf.msaa_layout == ISL_MSAA_LAYOUT_NONE ||
- mt->num_samples <= 1);
+ mt->num_samples == 1);
intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS,
0, INTEL_REMAINING_LAYERS, false, false);
@@ -3031,7 +3037,7 @@ intel_miptree_map_blit(struct brw_context *brw,
/* first_level */ 0,
/* last_level */ 0,
map->w, map->h, 1,
- /* samples */ 0,
+ /* samples */ 1,
MIPTREE_LAYOUT_TILING_NONE);
if (!map->linear_mt) {
@@ -3573,7 +3579,7 @@ intel_miptree_map(struct brw_context *brw,
{
struct intel_miptree_map *map;
- assert(mt->num_samples <= 1);
+ assert(mt->num_samples == 1 || mt->surf.samples == 1);
map = intel_miptree_attach_map(mt, level, slice, x, y, w, h, mode);
if (!map){
@@ -3619,7 +3625,7 @@ intel_miptree_unmap(struct brw_context *brw,
{
struct intel_miptree_map *map = mt->level[level].slice[slice].map;
- assert(mt->num_samples <= 1);
+ assert(mt->num_samples == 1 || mt->surf.samples == 1);
if (!map)
return;
@@ -3788,7 +3794,7 @@ intel_miptree_get_isl_surf(struct brw_context *brw,
}
surf->levels = mt->last_level - mt->first_level + 1;
- surf->samples = MAX2(mt->num_samples, 1);
+ surf->samples = mt->num_samples;
surf->size = 0; /* TODO */
surf->alignment = 0; /* TODO */
diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c
index f6cdb017c7..82e25fc5ea 100644
--- a/src/mesa/drivers/dri/i965/intel_tex.c
+++ b/src/mesa/drivers/dri/i965/intel_tex.c
@@ -94,7 +94,7 @@ intel_alloc_texture_image_buffer(struct gl_context *ctx,
} else {
intel_image->mt = intel_miptree_create_for_teximage(brw, intel_texobj,
intel_image,
- 0);
+ 1 /* samples */);
/* Even if the object currently has a mipmap tree associated
* with it, this one is a more likely candidate to represent the
@@ -147,7 +147,7 @@ intel_alloc_texture_storage(struct gl_context *ctx,
first_image->TexFormat,
0, levels - 1,
width, height, depth,
- num_samples,
+ MAX2(num_samples, 1),
MIPTREE_LAYOUT_TILING_ANY);
if (intel_texobj->mt == NULL) {
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 26ea9a5983..992d0903da 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -127,7 +127,7 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
width,
height,
depth,
- intelImage->base.Base.NumSamples,
+ MAX2(intelImage->base.Base.NumSamples, 1),
layout_flags | MIPTREE_LAYOUT_TILING_ANY);
}
diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index 08cf3bf7dc..a156f73097 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -146,7 +146,7 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
width,
height,
depth,
- 0 /* num_samples */,
+ 1 /* num_samples */,
layout_flags);
if (!intelObj->mt)
return;
--
2.11.0
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