[Mesa-dev] [v2 2/22] i965/miptree: Switch to isl_surf::samples
Jason Ekstrand
jason at jlekstrand.net
Wed Jul 19 20:28:25 UTC 2017
This and precursor patches
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
On Wed, Jul 19, 2017 at 12:43 PM, Topi Pohjolainen <
topi.pohjolainen at gmail.com> wrote:
> v2 (Jason):
> - Don't trigger miptree re-creation in vain later on with ISL
> based. Core GL uses zero to indicate single sampled while
> ISL uses one - this would cause intel_miptree_match_image()
> to always fail.
> - Now that native miptree is already using sample number of
> one, there is no need for MAX2() when converting to ISL.
>
> Reviewed-by: Jason Ekstrand <jason at jlekstrand.net> (v1)
> Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v1)
> Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 16 ++++-----
> src/mesa/drivers/dri/i965/brw_context.c | 2 +-
> src/mesa/drivers/dri/i965/brw_meta_util.c | 2 +-
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 4 +--
> src/mesa/drivers/dri/i965/brw_wm.c | 4 +--
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +-
> src/mesa/drivers/dri/i965/intel_blit.c | 4 +--
> src/mesa/drivers/dri/i965/intel_fbo.c | 4 +--
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 46
> ++++++++++++------------
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 ----
> src/mesa/drivers/dri/i965/intel_pixel_copy.c | 2 +-
> 11 files changed, 43 insertions(+), 49 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 2776872d92..474dfc61c1 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -135,7 +135,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
> struct isl_surf tmp_surfs[1])
> {
> if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
> - const unsigned num_samples = mt->num_samples;
> + const unsigned num_samples = mt->surf.samples;
> for (unsigned i = 0; i < num_layers; i++) {
> for (unsigned s = 0; s < num_samples; s++) {
> const unsigned phys_layer = (start_layer + i) * num_samples +
> s;
> @@ -275,7 +275,7 @@ swizzle_to_scs(GLenum swizzle)
> * Note: if the src (or dst) is a 2D multisample array texture on Gen7+
> using
> * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer)
> is
> * the physical layer holding sample 0. So, for example, if
> - * src_mt->num_samples == 4, then logical layer n corresponds to
> src_layer ==
> + * src_mt->surf.samples == 4, then logical layer n corresponds to
> src_layer ==
> * 4*n.
> */
> void
> @@ -296,9 +296,9 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
> "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
> __func__,
> - src_mt->num_samples, _mesa_get_format_name(src_mt->format),
> src_mt,
> + src_mt->surf.samples, _mesa_get_format_name(src_mt->format),
> src_mt,
> src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
> - dst_mt->num_samples, _mesa_get_format_name(dst_mt->format),
> dst_mt,
> + dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format),
> dst_mt,
> dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
> mirror_x, mirror_y);
>
> @@ -318,7 +318,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> * R32_FLOAT, so only the contents of the red channel matters.
> */
> if (brw->gen == 6 &&
> - src_mt->num_samples > 1 && dst_mt->num_samples <= 1 &&
> + src_mt->surf.samples > 1 && dst_mt->surf.samples <= 1 &&
> src_mt->format == dst_mt->format &&
> (dst_format == MESA_FORMAT_L_FLOAT32 ||
> dst_format == MESA_FORMAT_I_FLOAT32)) {
> @@ -375,9 +375,9 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
> DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
> "to %dx %s mt %p %d %d (%d,%d)\n",
> __func__,
> - src_mt->num_samples, _mesa_get_format_name(src_mt->format),
> src_mt,
> + src_mt->surf.samples, _mesa_get_format_name(src_mt->format),
> src_mt,
> src_level, src_layer, src_x, src_y, src_width, src_height,
> - dst_mt->num_samples, _mesa_get_format_name(dst_mt->format),
> dst_mt,
> + dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format),
> dst_mt,
> dst_level, dst_layer, dst_x, dst_y);
>
> struct isl_surf tmp_surfs[2];
> @@ -564,7 +564,7 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
> struct intel_mipmap_tree *dst_mt = intel_image->mt;
>
> /* There is support for only up to eight samples. */
> - if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
> + if (src_mt->surf.samples > 8 || dst_mt->surf.samples > 8)
> return false;
>
> if (_mesa_get_format_base_format(src_rb->Format) !=
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> b/src/mesa/drivers/dri/i965/brw_context.c
> index 303c658543..0ef601d342 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -1218,7 +1218,7 @@ intel_resolve_for_dri2_flush(struct brw_context
> *brw,
> rb = intel_get_renderbuffer(fb, buffers[i]);
> if (rb == NULL || rb->mt == NULL)
> continue;
> - if (rb->mt->num_samples == 1) {
> + if (rb->mt->surf.samples == 1) {
> assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
> rb->layer_count == 1);
> intel_miptree_prepare_access(brw, rb->mt, 0, 1, 0, 1, false,
> false);
> diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c
> b/src/mesa/drivers/dri/i965/brw_meta_util.c
> index 7b5a11811b..ea14f44790 100644
> --- a/src/mesa/drivers/dri/i965/brw_meta_util.c
> +++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
> @@ -298,7 +298,7 @@ brw_is_color_fast_clear_compatible(struct brw_context
> *brw,
> * fast clear because it's very likely to be immediately resolved.
> */
> if (brw->gen >= 9 &&
> - mt->num_samples == 1 &&
> + mt->surf.samples == 1 &&
> ctx->Color.sRGBEnabled &&
> _mesa_get_srgb_format_linear(mt->format) != mt->format)
> return false;
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> index 91e94ee4a0..5be73282dc 100644
> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> @@ -100,7 +100,7 @@ intel_vertical_texture_alignment_unit(struct
> brw_context *brw,
> if (brw->gen >= 8)
> return 4;
>
> - if (mt->num_samples > 1)
> + if (mt->surf.samples > 1)
> return 4;
>
> GLenum base_format = _mesa_get_format_base_format(mt->format);
> @@ -521,7 +521,7 @@ brw_miptree_choose_tiling(struct brw_context *brw,
> return I915_TILING_NONE;
> }
>
> - if (mt->num_samples > 1) {
> + if (mt->surf.samples > 1) {
> /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
> * Surface"):
> *
> diff --git a/src/mesa/drivers/dri/i965/brw_wm.c
> b/src/mesa/drivers/dri/i965/brw_wm.c
> index 9e1dcee8fd..c9c4504590 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm.c
> @@ -398,12 +398,12 @@ brw_populate_sampler_prog_key_data(struct
> gl_context *ctx,
> */
> if (intel_tex->mt->aux_usage == ISL_AUX_USAGE_MCS) {
> assert(brw->gen >= 7);
> - assert(intel_tex->mt->num_samples > 1);
> + assert(intel_tex->mt->surf.samples > 1);
> assert(intel_tex->mt->mcs_buf);
> assert(intel_tex->mt->surf.msaa_layout ==
> ISL_MSAA_LAYOUT_ARRAY);
> key->compressed_multisample_layout_mask |= 1 << s;
>
> - if (intel_tex->mt->num_samples >= 16) {
> + if (intel_tex->mt->surf.samples >= 16) {
> assert(brw->gen >= 9);
> key->msaa_16 |= 1 << s;
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 67dc9d8943..00f0a72b1f 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -1036,7 +1036,7 @@ gen4_update_renderbuffer_surface(struct brw_context
> *brw,
> surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
> (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
>
> - surf[4] = brw_get_surface_num_multisamples(mt->num_samples);
> + surf[4] = brw_get_surface_num_multisamples(mt->surf.samples);
>
> assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
> /* Note that the low bits of these fields are missing, so
> diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
> b/src/mesa/drivers/dri/i965/intel_blit.c
> index 2471380a0a..226c4f23b7 100644
> --- a/src/mesa/drivers/dri/i965/intel_blit.c
> +++ b/src/mesa/drivers/dri/i965/intel_blit.c
> @@ -298,7 +298,7 @@ intel_miptree_blit(struct brw_context *brw,
> GLenum logicop)
> {
> /* The blitter doesn't understand multisampling at all. */
> - if (src_mt->num_samples > 1 || dst_mt->num_samples > 1)
> + if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1)
> return false;
>
> /* No sRGB decode or encode is done by the hardware blitter, which is
> @@ -371,7 +371,7 @@ intel_miptree_copy(struct brw_context *brw,
> uint32_t src_width, uint32_t src_height)
> {
> /* The blitter doesn't understand multisampling at all. */
> - if (src_mt->num_samples > 1 || dst_mt->num_samples > 1)
> + if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1)
> return false;
>
> if (src_mt->format == MESA_FORMAT_S_UINT8)
> diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
> b/src/mesa/drivers/dri/i965/intel_fbo.c
> index b7de49f22e..87dc32673c 100644
> --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> @@ -533,7 +533,7 @@ intel_renderbuffer_update_wrapper(struct brw_context
> *brw,
> irb->mt_layer = layer;
>
> const unsigned layer_multiplier =
> - mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY ? mt->num_samples : 1;
> + mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY ? mt->surf.samples :
> 1;
>
> if (!layered) {
> irb->layer_count = 1;
> @@ -970,7 +970,7 @@ intel_renderbuffer_move_to_temp(struct brw_context
> *brw,
> intel_image->base.Base.TexFormat,
> 0, 0,
> width, height, 1,
> - irb->mt->num_samples,
> + irb->mt->surf.samples,
> layout_flags);
>
> if (!invalidate)
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 338e965737..418ec3cf06 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -168,7 +168,7 @@ intel_miptree_supports_ccs(struct brw_context *brw,
> return false;
>
> /* This function applies only to non-multisampled render targets. */
> - if (mt->num_samples > 1)
> + if (mt->surf.samples > 1)
> return false;
>
> /* MCS is only supported for color buffers */
> @@ -191,7 +191,7 @@ intel_miptree_supports_ccs(struct brw_context *brw,
> * accidentally reject a multisampled surface here. We should have
> * rejected it earlier by explicitly checking the sample count.
> */
> - assert(mt->num_samples == 1);
> + assert(mt->surf.samples == 1);
> }
>
> /* Handle the hardware restrictions...
> @@ -384,7 +384,7 @@ intel_miptree_create_layout(struct brw_context *brw,
> mt->supports_fast_clear = false;
> mt->aux_state = NULL;
> mt->cpp = _mesa_get_format_bytes(format);
> - mt->num_samples = num_samples;
> + mt->surf.samples = num_samples;
> mt->compressed = _mesa_is_format_compressed(format);
> mt->surf.msaa_layout = ISL_MSAA_LAYOUT_NONE;
> mt->refcount = 1;
> @@ -604,7 +604,7 @@ intel_miptree_choose_aux_usage(struct brw_context
> *brw,
> assert(mt->aux_usage == ISL_AUX_USAGE_NONE);
>
> const unsigned no_flags = 0;
> - if (mt->num_samples > 1 && is_mcs_supported(brw, mt->format,
> no_flags)) {
> + if (mt->surf.samples > 1 && is_mcs_supported(brw, mt->format,
> no_flags)) {
> assert(mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
> mt->aux_usage = ISL_AUX_USAGE_MCS;
> } else if (intel_tiling_supports_ccs(brw, mt->tiling) &&
> @@ -1369,8 +1369,8 @@ intel_miptree_match_image(struct intel_mipmap_tree
> *mt,
> }
>
> int level_depth = mt->level[level].depth;
> - if (mt->num_samples > 1 && mt->surf.msaa_layout ==
> ISL_MSAA_LAYOUT_ARRAY)
> - level_depth /= mt->num_samples;
> + if (mt->surf.samples > 1 && mt->surf.msaa_layout ==
> ISL_MSAA_LAYOUT_ARRAY)
> + level_depth /= mt->surf.samples;
>
> /* Test image dimensions against the base level image adjusted for
> * minification. This will also catch images not present in the
> @@ -1383,7 +1383,7 @@ intel_miptree_match_image(struct intel_mipmap_tree
> *mt,
> }
>
> /* Core uses sample number of zero to indicate single-sampled. */
> - if (MAX2(image->NumSamples, 1) != mt->num_samples)
> + if (MAX2(image->NumSamples, 1) != mt->surf.samples)
> return false;
>
> return true;
> @@ -2004,8 +2004,8 @@ intel_miptree_alloc_aux(struct brw_context *brw,
>
> case ISL_AUX_USAGE_MCS:
> assert(_mesa_is_format_color_format(mt->format));
> - assert(mt->num_samples > 1);
> - if (!intel_miptree_alloc_mcs(brw, mt, mt->num_samples))
> + assert(mt->surf.samples > 1);
> + if (!intel_miptree_alloc_mcs(brw, mt, mt->surf.samples))
> return false;
> return true;
>
> @@ -2017,7 +2017,7 @@ intel_miptree_alloc_aux(struct brw_context *brw,
>
> case ISL_AUX_USAGE_CCS_E:
> assert(_mesa_is_format_color_format(mt->format));
> - assert(mt->num_samples == 1);
> + assert(mt->surf.samples == 1);
> if (!intel_miptree_alloc_ccs(brw, mt))
> return false;
> return true;
> @@ -2066,7 +2066,7 @@ intel_miptree_sample_with_hiz(struct brw_context
> *brw,
> * There is no such blurb for 1D textures, but there is sufficient
> evidence
> * that this is broken on SKL+.
> */
> - return (mt->num_samples == 1 &&
> + return (mt->surf.samples == 1 &&
> mt->target != GL_TEXTURE_3D &&
> mt->target != GL_TEXTURE_1D /* gen9+ restriction */);
> }
> @@ -2126,7 +2126,7 @@ intel_miptree_check_color_resolve(const struct
> brw_context *brw,
> (level == 0 && mt->first_level == 0 && mt->last_level == 0));
>
> /* Compression of arrayed msaa surfaces is supported. */
> - if (mt->num_samples > 1)
> + if (mt->surf.samples > 1)
> return;
>
> /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
> @@ -2466,7 +2466,7 @@ intel_miptree_prepare_access(struct brw_context
> *brw,
> if (!mt->mcs_buf)
> return;
>
> - if (mt->num_samples > 1) {
> + if (mt->surf.samples > 1) {
> /* Nothing to do for MSAA */
> assert(aux_supported && fast_clear_supported);
> } else {
> @@ -2515,7 +2515,7 @@ intel_miptree_finish_write(struct brw_context *brw,
> if (!mt->mcs_buf)
> return;
>
> - if (mt->num_samples > 1) {
> + if (mt->surf.samples > 1) {
> for (uint32_t a = 0; a < num_layers; a++) {
> intel_miptree_finish_mcs_write(brw, mt, level, start_layer +
> a,
> written_with_aux);
> @@ -2547,7 +2547,7 @@ intel_miptree_get_aux_state(const struct
> intel_mipmap_tree *mt,
>
> if (_mesa_is_format_color_format(mt->format)) {
> assert(mt->mcs_buf != NULL);
> - assert(mt->num_samples == 1 ||
> + assert(mt->surf.samples == 1 ||
> mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
> } else if (mt->format == MESA_FORMAT_S_UINT8) {
> unreachable("Cannot get aux state for stencil");
> @@ -2568,7 +2568,7 @@ intel_miptree_set_aux_state(struct brw_context *brw,
>
> if (_mesa_is_format_color_format(mt->format)) {
> assert(mt->mcs_buf != NULL);
> - assert(mt->num_samples == 1 ||
> + assert(mt->surf.samples == 1 ||
> mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
> } else if (mt->format == MESA_FORMAT_S_UINT8) {
> unreachable("Cannot get aux state for stencil");
> @@ -2623,7 +2623,7 @@ intel_miptree_prepare_texture_slices(struct
> brw_context *brw,
> {
> bool aux_supported, clear_supported;
> if (_mesa_is_format_color_format(mt->format)) {
> - if (mt->num_samples > 1) {
> + if (mt->surf.samples > 1) {
> aux_supported = clear_supported = true;
> } else {
> aux_supported = can_texture_with_ccs(brw, mt, view_format);
> @@ -2690,7 +2690,7 @@ intel_miptree_prepare_render(struct brw_context
> *brw,
> * enabled because otherwise the surface state will be programmed with
> * the linear equivalent format anyway.
> */
> - if (brw->gen == 9 && srgb_enabled && mt->num_samples == 1 &&
> + if (brw->gen == 9 && srgb_enabled && mt->surf.samples == 1 &&
> _mesa_get_srgb_format_linear(mt->format) != mt->format) {
>
> /* Lossless compression is not supported for SRGB formats, it
> @@ -2753,7 +2753,7 @@ intel_miptree_make_shareable(struct brw_context
> *brw,
> * reached for multisample buffers.
> */
> assert(mt->surf.msaa_layout == ISL_MSAA_LAYOUT_NONE ||
> - mt->num_samples == 1);
> + mt->surf.samples == 1);
>
> intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS,
> 0, INTEL_REMAINING_LAYERS, false, false);
> @@ -2931,7 +2931,7 @@ intel_update_r8stencil(struct brw_context *brw,
> src->logical_width0,
> src->logical_height0,
> src->logical_depth0,
> - src->num_samples,
> + src->surf.samples,
> r8stencil_flags);
> assert(mt->r8stencil_mt);
> }
> @@ -3579,7 +3579,7 @@ intel_miptree_map(struct brw_context *brw,
> {
> struct intel_miptree_map *map;
>
> - assert(mt->num_samples == 1 || mt->surf.samples == 1);
> + assert(mt->surf.samples == 1);
>
> map = intel_miptree_attach_map(mt, level, slice, x, y, w, h, mode);
> if (!map){
> @@ -3625,7 +3625,7 @@ intel_miptree_unmap(struct brw_context *brw,
> {
> struct intel_miptree_map *map = mt->level[level].slice[slice].map;
>
> - assert(mt->num_samples == 1 || mt->surf.samples == 1);
> + assert(mt->surf.samples == 1);
>
> if (!map)
> return;
> @@ -3794,7 +3794,7 @@ intel_miptree_get_isl_surf(struct brw_context *brw,
> }
>
> surf->levels = mt->last_level - mt->first_level + 1;
> - surf->samples = mt->num_samples;
> + surf->samples = mt->surf.samples;
>
> surf->size = 0; /* TODO */
> surf->alignment = 0; /* TODO */
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index 89590d2ba2..fde9a022fd 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -414,12 +414,6 @@ struct intel_mipmap_tree
> /** Bytes per pixel (or bytes per block if compressed) */
> GLuint cpp;
>
> - /**
> - * @see RENDER_SURFACE_STATE.NumberOfMultisamples
> - * @see 3DSTATE_MULTISAMPLE.NumberOfMultisamples
> - */
> - GLuint num_samples;
> -
> bool compressed;
>
> /**
> diff --git a/src/mesa/drivers/dri/i965/intel_pixel_copy.c
> b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
> index 3ffd68c048..3f8df3002f 100644
> --- a/src/mesa/drivers/dri/i965/intel_pixel_copy.c
> +++ b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
> @@ -101,7 +101,7 @@ do_blit_copypixels(struct gl_context * ctx,
> return false;
> }
>
> - if (draw_irb->mt->num_samples > 1 || read_irb->mt->num_samples > 1) {
> + if (draw_irb->mt->surf.samples > 1 || read_irb->mt->surf.samples > 1) {
> perf_debug("glCopyPixels() fallback: multisampled buffers\n");
> return false;
> }
> --
> 2.11.0
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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