[Mesa-dev] [PATCH 3/6] i965/miptree: Use isl_image_offset in get_tile_offsets()
Topi Pohjolainen
topi.pohjolainen at gmail.com
Wed Jul 26 19:28:35 UTC 2017
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 54 ++++++++++++++----------
src/mesa/drivers/dri/i965/intel_fbo.h | 14 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 28 ++++++------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 8 ++--
src/mesa/drivers/dri/i965/intel_screen.c | 9 ++--
5 files changed, 61 insertions(+), 52 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index abf1d29678..2da0984c0f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -77,8 +77,7 @@ uint32_t rb_mocs[] = {
static void
get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt,
GLenum target, struct isl_view *view,
- uint32_t *tile_x, uint32_t *tile_y,
- uint32_t *offset, struct isl_surf *surf)
+ struct isl_image_offset *surf_offset, struct isl_surf *surf)
{
*surf = mt->surf;
@@ -99,11 +98,12 @@ get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt,
*/
assert(brw->has_surface_tile_offset);
assert(view->levels == 1 && view->array_len == 1);
- assert(*tile_x == 0 && *tile_y == 0 && *offset == 0);
+ assert(surf_offset->intra_tile_x == 0 &&
+ surf_offset->intra_tile_y == 0 &&
+ surf_offset->tile_aligned_byte_offset == 0);
- *offset = intel_miptree_get_tile_offsets(mt, view->base_level,
- view->base_array_layer,
- tile_x, tile_y);
+ intel_miptree_get_tile_offsets(mt, view->base_level,
+ view->base_array_layer, surf_offset);
/* Minify the logical dimensions of the texture. */
const unsigned l = view->base_level - mt->first_level;
@@ -135,13 +135,15 @@ brw_emit_surface_state(struct brw_context *brw,
uint32_t mocs, uint32_t *surf_offset, int surf_index,
unsigned read_domains, unsigned write_domains)
{
- uint32_t tile_x = mt->level[0].level_x;
- uint32_t tile_y = mt->level[0].level_y;
- uint32_t offset = mt->offset;
+ struct isl_image_offset offset = {
+ .tile_aligned_byte_offset = mt->offset,
+ .intra_tile_x = mt->level[0].level_x,
+ .intra_tile_y = mt->level[0].level_y
+ };
struct isl_surf surf;
- get_isl_surf(brw, mt, target, &view, &tile_x, &tile_y, &offset, &surf);
+ get_isl_surf(brw, mt, target, &view, &offset, &surf);
union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
@@ -180,14 +182,17 @@ brw_emit_surface_state(struct brw_context *brw,
surf_offset);
isl_surf_fill_state(&brw->isl_dev, state, .surf = &mt->surf, .view = &view,
- .address = mt->bo->offset64 + offset,
+ .address = mt->bo->offset64 +
+ offset.tile_aligned_byte_offset,
.aux_surf = aux_surf, .aux_usage = aux_usage,
.aux_address = aux_offset,
.mocs = mocs, .clear_color = clear_color,
- .x_offset_sa = tile_x, .y_offset_sa = tile_y);
+ .x_offset_sa = offset.intra_tile_x,
+ .y_offset_sa = offset.intra_tile_y);
brw_emit_reloc(&brw->batch, *surf_offset + brw->isl_dev.ss.addr_offset,
- mt->bo, offset, read_domains, write_domains);
+ mt->bo, offset.tile_aligned_byte_offset,
+ read_domains, write_domains);
if (aux_surf) {
/* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the
@@ -938,7 +943,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
uint32_t *surf;
- uint32_t tile_x, tile_y;
+ struct isl_image_offset image_offset;
enum isl_format format;
uint32_t offset;
/* _NEW_BUFFERS */
@@ -949,9 +954,9 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
assert(!(flags & INTEL_AUX_BUFFER_DISABLED));
if (rb->TexImage && !brw->has_surface_tile_offset) {
- intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y);
+ intel_renderbuffer_get_tile_offsets(irb, &image_offset);
- if (tile_x != 0 || tile_y != 0) {
+ if (image_offset.intra_tile_x != 0 || image_offset.intra_tile_y != 0) {
/* Original gen4 hardware couldn't draw to a non-tile-aligned
* destination in a miptree unless you actually setup your renderbuffer
* as a miptree and used the fragile lod/array_index/etc. controls to
@@ -975,9 +980,10 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
format << BRW_SURFACE_FORMAT_SHIFT);
+ intel_renderbuffer_get_tile_offsets(irb, &image_offset);
+
/* reloc */
- surf[1] = intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
- mt->bo->offset64;
+ surf[1] = image_offset.tile_aligned_byte_offset + mt->bo->offset64;
surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
@@ -987,14 +993,16 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
surf[4] = brw_get_surface_num_multisamples(mt->surf.samples);
- assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
+ assert(brw->has_surface_tile_offset ||
+ (image_offset.intra_tile_x == 0 &&
+ image_offset.intra_tile_y == 0));
/* Note that the low bits of these fields are missing, so
* there's the possibility of getting in trouble.
*/
- assert(tile_x % 4 == 0);
- assert(tile_y % 2 == 0);
- surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
- (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
+ assert(image_offset.intra_tile_x % 4 == 0);
+ assert(image_offset.intra_tile_y % 2 == 0);
+ surf[5] = ((image_offset.intra_tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
+ (image_offset.intra_tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
(mt->surf.image_alignment_el.height == 4 ?
BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h b/src/mesa/drivers/dri/i965/intel_fbo.h
index 1e2494286b..b5d0a0e044 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.h
+++ b/src/mesa/drivers/dri/i965/intel_fbo.h
@@ -198,19 +198,17 @@ intel_fbo_init(struct brw_context *brw);
void
intel_renderbuffer_set_draw_offset(struct intel_renderbuffer *irb);
-static inline uint32_t
+static inline void
intel_renderbuffer_get_tile_offsets(struct intel_renderbuffer *irb,
- uint32_t *tile_x,
- uint32_t *tile_y)
+ struct isl_image_offset *image_offset)
{
if (irb->align_wa_mt) {
- *tile_x = 0;
- *tile_y = 0;
- return 0;
+ memset(image_offset, 0, sizeof(*image_offset));
+ return;
}
- return intel_miptree_get_tile_offsets(irb->mt, irb->mt_level, irb->mt_layer,
- tile_x, tile_y);
+ intel_miptree_get_tile_offsets(irb->mt, irb->mt_level, irb->mt_layer,
+ image_offset);
}
bool
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 1b42edd285..37024c011d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -969,10 +969,10 @@ intel_miptree_create_for_dri_image(struct brw_context *brw,
* trouble resolving back to destination image due to alignment issues.
*/
if (!brw->has_surface_tile_offset) {
- uint32_t draw_x, draw_y;
- intel_miptree_get_tile_offsets(mt, 0, 0, &draw_x, &draw_y);
+ struct isl_image_offset image_offset;
+ intel_miptree_get_tile_offsets(mt, 0, 0, &image_offset);
- if (draw_x != 0 || draw_y != 0) {
+ if (image_offset.intra_tile_x != 0 || image_offset.intra_tile_y != 0) {
_mesa_error(&brw->ctx, GL_INVALID_OPERATION, __func__);
intel_miptree_release(&mt);
return NULL;
@@ -1337,20 +1337,20 @@ intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
* according to the tiling restrictions, plus any required x/y offset
* from there.
*/
-uint32_t
+void
intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
- GLuint level, GLuint slice,
- uint32_t *tile_x,
- uint32_t *tile_y)
+ unsigned level, unsigned slice,
+ struct isl_image_offset *image_offset)
{
/* First consider the special case where caller wants the very first slice.
* In such case there is only possible import offset to consider. This
* consists of tile aligned byte offset and intra tile x,y coordinates.
*/
if (level == 0 && slice == 0) {
- *tile_x = mt->level[0].level_x;
- *tile_y = mt->level[0].level_y;
- return mt->offset;
+ image_offset->intra_tile_x = mt->level[0].level_x;
+ image_offset->intra_tile_y = mt->level[0].level_y;
+ image_offset->tile_aligned_byte_offset = mt->offset;
+ return;
}
/* Only single slices can be imported - mipmapped and arrayed always
@@ -1366,10 +1366,10 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
intel_get_tile_masks(mt->surf.tiling, mt->cpp, &mask_x, &mask_y);
intel_miptree_get_image_offset(mt, level, slice, &x, &y);
- *tile_x = x & mask_x;
- *tile_y = y & mask_y;
-
- return intel_miptree_get_aligned_offset(mt, x & ~mask_x, y & ~mask_y);
+ image_offset->intra_tile_x = x & mask_x;
+ image_offset->intra_tile_y = y & mask_y;
+ image_offset->tile_aligned_byte_offset =
+ intel_miptree_get_aligned_offset(mt, x & ~mask_x, y & ~mask_y);
}
static void
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 3628345c4e..b8d36b35e0 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -463,11 +463,11 @@ void
intel_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
uint32_t *tile_w, uint32_t *tile_h);
-uint32_t
+void
intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt,
- GLuint level, GLuint slice,
- uint32_t *tile_x,
- uint32_t *tile_y);
+ unsigned level, unsigned slice,
+ struct isl_image_offset *image_offset);
+
uint32_t
intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
uint32_t x, uint32_t y);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 5adb8ef1f6..78dce97706 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -417,9 +417,12 @@ intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image,
level - mt->first_level);
image->pitch = mt->surf.row_pitch;
- image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,
- &image->tile_x,
- &image->tile_y);
+ struct isl_image_offset image_offset;
+ intel_miptree_get_tile_offsets(mt, level, zoffset, &image_offset);
+
+ image->offset = image_offset.tile_aligned_byte_offset;
+ image->tile_x = image_offset.intra_tile_x;
+ image->tile_y = image_offset.intra_tile_y;
brw_bo_unreference(image->bo);
image->bo = mt->bo;
--
2.11.0
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