[Mesa-dev] [PATCH 02/14] ac/surface: remove RADEON_SURF_HAS_TILE_MODE_INDEX

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

it's useless
---
 src/amd/common/ac_surface.h                        | 1 -
 src/amd/vulkan/radv_image.c                        | 1 -
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 3 ---
 3 files changed, 5 deletions(-)

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index ee96003..3c9e13e 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -55,21 +55,20 @@ enum radeon_micro_mode {
     RADEON_MICRO_MODE_DEPTH = 2,
     RADEON_MICRO_MODE_ROTATED = 3,
 };
 
 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
 #define RADEON_SURF_SCANOUT                     (1 << 16)
 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 #define RADEON_SURF_SBUFFER                     (1 << 18)
 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
-#define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 #define RADEON_SURF_FMASK                       (1 << 21)
 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 #define RADEON_SURF_IMPORTED                    (1 << 24)
 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
 
 struct legacy_surf_level {
     uint64_t                    offset;
     uint64_t                    slice_size;
     uint64_t                    dcc_offset;
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 4b47e17..499287d 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -101,21 +101,20 @@ radv_init_surface(struct radv_device *device,
 		unreachable("unhandled image type");
 	}
 
 	if (is_depth) {
 		surface->flags |= RADEON_SURF_ZBUFFER;
 	}
 
 	if (is_stencil)
 		surface->flags |= RADEON_SURF_SBUFFER;
 
-	surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
 	surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
 
 	if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
 	                           VK_IMAGE_USAGE_STORAGE_BIT)) ||
 	    (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
             (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
             device->physical_device->rad_info.chip_class < VI ||
             create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
             !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
 		surface->flags |= RADEON_SURF_DISABLE_DCC;
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index eaa978e..e3ccb81 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -35,23 +35,20 @@
 #include "radv_amdgpu_surface.h"
 #include "sid.h"
 
 #include "ac_surface.h"
 
 static int radv_amdgpu_surface_sanity(const struct ac_surf_info *surf_info,
 				      const struct radeon_surf *surf)
 {
 	unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
 
-	if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
-		return -EINVAL;
-
 	if (!surf->blk_w || !surf->blk_h)
 		return -EINVAL;
 
 	switch (type) {
 	case RADEON_SURF_TYPE_1D:
 		if (surf_info->height > 1)
 			return -EINVAL;
 		/* fall through */
 	case RADEON_SURF_TYPE_2D:
 	case RADEON_SURF_TYPE_CUBEMAP:
-- 
2.7.4