[Mesa-dev] [PATCH 03/14] ac/surface: add RADEON_SURF_SHAREABLE

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

Shareable textures won't use tile swizzle.
---
 src/amd/common/ac_surface.h               | 1 +
 src/gallium/drivers/radeon/r600_texture.c | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 3c9e13e..01a71f3 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -60,20 +60,21 @@ enum radeon_micro_mode {
 #define RADEON_SURF_SCANOUT                     (1 << 16)
 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 #define RADEON_SURF_SBUFFER                     (1 << 18)
 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
 #define RADEON_SURF_FMASK                       (1 << 21)
 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 #define RADEON_SURF_IMPORTED                    (1 << 24)
 #define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
+#define RADEON_SURF_SHAREABLE                   (1 << 26)
 
 struct legacy_surf_level {
     uint64_t                    offset;
     uint64_t                    slice_size;
     uint64_t                    dcc_offset;
     uint64_t                    dcc_fast_clear_size;
     uint16_t                    nblk_x;
     uint16_t                    nblk_y;
     enum radeon_surf_mode       mode;
 };
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 3aac3c7..2d58dc9 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -273,22 +273,24 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
 		/* This should catch bugs in gallium users setting incorrect flags. */
 		assert(ptex->nr_samples <= 1 &&
 		       ptex->array_size == 1 &&
 		       ptex->depth0 == 1 &&
 		       ptex->last_level == 0 &&
 		       !(flags & RADEON_SURF_Z_OR_SBUFFER));
 
 		flags |= RADEON_SURF_SCANOUT;
 	}
 
+	if (ptex->bind & PIPE_BIND_SHARED)
+		flags |= RADEON_SURF_SHAREABLE;
 	if (is_imported)
-		flags |= RADEON_SURF_IMPORTED;
+		flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
 	if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
 		flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
 
 	r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe,
 				      array_mode, surface);
 	if (r) {
 		return r;
 	}
 
 	if (rscreen->chip_class >= GFX9) {
-- 
2.7.4