[Mesa-dev] [PATCH 09/14] ac/surface: align DCC size for surfaces that use tile swizzle

Marek Olšák maraeo at gmail.com
Mon Jul 31 23:40:32 UTC 2017


From: Marek Olšák <marek.olsak at amd.com>

Note that dcc_alignment = pipe_interleave_bytes * num_pipes * num_banks,
which is greater than the previous open-coded alignment.
---
 src/amd/common/ac_surface.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 3716d3d..823a65d 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -727,23 +727,30 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 				}
 			}
 		}
 	}
 
 	/* Recalculate the whole DCC miptree size including disabled levels.
 	 * This is what addrlib does, but calling addrlib would be a lot more
 	 * complicated.
 	 */
 	if (surf->dcc_size && config->info.levels > 1) {
+		/* The smallest miplevels that are never compressed by DCC
+		 * still read the DCC buffer via TC if the base level uses DCC,
+		 * and for some reason the DCC buffer needs to be larger if
+		 * the miptree uses non-zero tile_swizzle. Otherwise there are
+		 * VM faults.
+		 *
+		 * "dcc_alignment * 4" was determined by trial and error.
+		 */
 		surf->dcc_size = align64(surf->surf_size >> 8,
-					 info->pipe_interleave_bytes *
-					 info->num_tile_pipes);
+					 surf->dcc_alignment * 4);
 	}
 
 	/* Make sure HTILE covers the whole miptree, because the shader reads
 	 * TC-compatible HTILE even for levels where it's disabled by DB.
 	 */
 	if (surf->htile_size && config->info.levels > 1)
 		surf->htile_size *= 2;
 
 	surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
 	return 0;
-- 
2.7.4



More information about the mesa-dev mailing list