[Mesa-dev] [PATCH 10/14] winsys/amdgpu: enable computation of tile swizzle

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 12 +++++++++++-
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h  |  2 ++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index d438b6d..99e4d77 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -85,19 +85,29 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
    struct ac_surf_config config;
 
    config.info.width = tex->width0;
    config.info.height = tex->height0;
    config.info.depth = tex->depth0;
    config.info.array_size = tex->array_size;
    config.info.samples = tex->nr_samples;
    config.info.levels = tex->last_level + 1;
    config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
    config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
-   config.info.surf_index = NULL;
+
+   /* Use different surface counters for color and FMASK, so that MSAA MRTs
+    * always use consecutive surface indices when FMASK is allocated between
+    * them.
+    */
+   if (flags & RADEON_SURF_FMASK)
+      config.info.surf_index = &ws->surf_index_fmask;
+   else if (!(flags & RADEON_SURF_Z_OR_SBUFFER))
+      config.info.surf_index = &ws->surf_index_color;
+   else
+      config.info.surf_index = NULL;
 
    return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf);
 }
 
 void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
 {
    ws->base.surface_init = amdgpu_surface_init;
 }
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
index 7cd2f20..7aca612 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
@@ -50,20 +50,22 @@ struct amdgpu_winsys {
    struct pipe_reference reference;
    struct pb_cache bo_cache;
    struct pb_slabs bo_slabs;
 
    amdgpu_device_handle dev;
 
    mtx_t bo_fence_lock;
 
    int num_cs; /* The number of command streams created. */
    unsigned num_total_rejected_cs;
+   uint32_t surf_index_color;
+   uint32_t surf_index_fmask;
    uint32_t next_bo_unique_id;
    uint64_t allocated_vram;
    uint64_t allocated_gtt;
    uint64_t mapped_vram;
    uint64_t mapped_gtt;
    uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
    uint64_t num_gfx_IBs;
    uint64_t num_sdma_IBs;
    uint64_t num_mapped_buffers;
    uint64_t gfx_bo_list_counter;
-- 
2.7.4