[Mesa-dev] [PATCH V2] i965: Rename brw_format variable names to isl_format
Jason Ekstrand
jason at jlekstrand.net
Thu Jun 1 16:53:36 UTC 2017
On Thu, Jun 1, 2017 at 9:41 AM, Anuj Phogat <anuj.phogat at gmail.com> wrote:
> On Tue, May 23, 2017 at 2:35 PM, Anuj Phogat <anuj.phogat at gmail.com>
> wrote:
> > This patch makes non functional changes. Renaming is just to
> > make the code more readable.
> >
> > V2: update the types to "enum isl_format"
> Jason, do you have any other questions ? r-b ?
>
Patch 1/6 of the series Chad sent out yesterday also does this and a bit
more. I don't think he saw yours.
> >
> > Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
> > Cc: Jason Ekstrand <jason at jlekstrand.net>
> > ---
> > src/mesa/drivers/dri/i965/brw_context.c | 5 +++--
> > src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 6 +++---
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +++--
> > 3 files changed, 9 insertions(+), 7 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> b/src/mesa/drivers/dri/i965/brw_context.c
> > index d3ed871..cb6a76a 100644
> > --- a/src/mesa/drivers/dri/i965/brw_context.c
> > +++ b/src/mesa/drivers/dri/i965/brw_context.c
> > @@ -205,9 +205,10 @@ intel_texture_view_requires_resolve(struct
> brw_context *brw,
> > !intel_miptree_is_lossless_compressed(brw, intel_tex->mt))
> > return false;
> >
> > - const uint32_t brw_format = brw_isl_format_for_mesa_
> format(intel_tex->_Format);
> > + const enum isl_format isl_format =
> > + brw_isl_format_for_mesa_format(intel_tex->_Format);
> >
> > - if (isl_format_supports_ccs_e(&brw->screen->devinfo, brw_format))
> > + if (isl_format_supports_ccs_e(&brw->screen->devinfo, isl_format))
> > return false;
> >
> > perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
> > diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > index a0fed60..05e41dc 100644
> > --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > @@ -686,7 +686,7 @@ brw_update_buffer_texture_surface(struct gl_context
> *ctx,
> > uint32_t size = tObj->BufferSize;
> > struct brw_bo *bo = NULL;
> > mesa_format format = tObj->_BufferObjectFormat;
> > - uint32_t brw_format = brw_isl_format_for_mesa_format(format);
> > + const enum isl_format isl_format = brw_isl_format_for_mesa_
> format(format);
> > int texel_size = _mesa_get_format_bytes(format);
> >
> > if (intel_obj) {
> > @@ -712,14 +712,14 @@ brw_update_buffer_texture_surface(struct
> gl_context *ctx,
> > */
> > size = MIN2(size, ctx->Const.MaxTextureBufferSize * (unsigned)
> texel_size);
> >
> > - if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
> > + if (isl_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
> > _mesa_problem(NULL, "bad format %s for texture buffer\n",
> > _mesa_get_format_name(format));
> > }
> >
> > brw_emit_buffer_surface_state(brw, surf_offset, bo,
> > tObj->BufferOffset,
> > - brw_format,
> > + isl_format,
> > size,
> > texel_size,
> > false /* rw */);
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > index db0a397..a92e3cb 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -209,8 +209,9 @@ intel_miptree_supports_non_msrt_fast_clear(struct
> brw_context *brw,
> >
> > if (brw->gen >= 9) {
> > mesa_format linear_format = _mesa_get_srgb_format_linear(
> mt->format);
> > - const uint32_t brw_format = brw_isl_format_for_mesa_
> format(linear_format);
> > - return isl_format_supports_ccs_e(&brw->screen->devinfo,
> brw_format);
> > + const enum isl_format isl_format =
> > + brw_isl_format_for_mesa_format(linear_format);
> > + return isl_format_supports_ccs_e(&brw->screen->devinfo,
> isl_format);
> > } else
> > return true;
> > }
> > --
> > 2.9.3
> >
>
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